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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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AK2401 Datenblatt(PDF) 23 Page - Asahi Kasei Microsystems |
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AK2401 Datenblatt(HTML) 23 Page - Asahi Kasei Microsystems |
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23 / 103 page  [AK2401] 017003093-E-00 2017/3 23 12.2. Power-up Sequence of PLL Synthesizer Figure 11. Power-up Sequence of PLL Synthesizer Write data to the registers in <Address 0x01 ~ 0x08>, synthesizer frequency settings will be valid when writing to the last address “0x08” of the setting. The synthesizer, clock buffer and reference circuits should be powered up when writing to the <Address 0x08>. Set PD_SYNTH_N, PD_CLKBUF_N and PD_REF_N bits = “1” in <Address 0x2E> to power on these circuits with a stable TCXO input before setting synthesizer frequency. (Refer to “13.1. Power Management ” for details) Wait 500µsec to stabilize the internal circuit after power on these circuits and execute register write to the <Address 0x08> to set synthesizer frequency. Writing to the <Address 0x08> will be a trigger of frequency change of the synthesizer. Fast Lock-up mode is enabled when the <Address 0x0C> FASTEN bit = “1”. Refer to “13.7.4. Fast Lock Function” for details of the mode. PLL Synthesizer Bias circuit <Address0x2E> PD_SYNTH_N bit PD_CLKBUF_N bit PD_REF_N bit <Address0x01~0x08> INT, FARC, MOD bits PLL Synthesizer Operation Do not care TCXOIN pin Stable PD_SYNTH_N, PD_CLKBUF_N, PD_REF_N bits can set "1" Unstable Stable Power Down 500μsec Unlock <0x08> accesible <0x08> Register access Register access (Fast) Lockup Lock Register access <0x01~0x07> can be accesss before PLL Synthesizer Bias circuit is stable |
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