Datenblatt-Suchmaschine für elektronische Bauteile |
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AK2401 Datenblatt(PDF) 90 Page - Asahi Kasei Microsystems |
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AK2401 Datenblatt(HTML) 90 Page - Asahi Kasei Microsystems |
90 / 103 page [AK2401] 017003093-E-00 2017/3 90 15.23. <0x2E>PD Address D7 D6 D5 D4 D3 D2 D1 D0 R/W 0x2E PD_ CLKBUF_N PD_ LNA_N PD_ RXR_N PD_ TXR_N PD_ SYNTH_N PD_ ADC_N PD_ DAC_N PD_ REF_N R/W Initial value 0 0 0 0 0 0 0 0 Control each block power down. Refer to “13.1. Power Management” for details. 15.24. <0x2F~0x30>READ PGA Address D7 D6 D5 D4 D3 D2 D1 D0 R/W 0x2F X R_LNA_ LGMODE RPGA_I[5:0] R Initial value 0 0 0 0 0 0 0 0x30 X X RPGA_Q[5:0] R Initial value 0 0 0 0 0 0 R_LNA_LGMODE: LNA Gain Mode Readback (Readback Only) Gain mode of the low noise amplifier is readback by writing the register addresses of this register. “0” indicates Normal Gain Mode and “1” indicates Low Gain Mode. AGC calculation result is readback when LNA_AGCOFF bit = “0”. The setting value of LNA_LGMODE bit will be readback when LNA_AGCOFF bit = “1”. RPGA_I[5:0]: Ich PGA Gain Readback (Readback Only) RPGA_Q[5:0]: Qch PGA Gain Readback (Readback Only) Setting gain of programmable gain amplifier is readback by writing the register addresses of these settings above. AGC calculation result is readback when AGCOFF bit = “0” <Address 0x1E>. The setting values of PGAGAIN_I[5:0] bits <Address 0x15> and PGAGAIN_Q[5:0] bits <Address 0x16> will be readback when AGCOFF bit = “1”. 15.25. <0x31~0x36>READ OFST Address D7 D6 D5 D4 D3 D2 D1 D0 R/W 0x31 R_OFST_I[23:16] R Initial value 0 0 0 0 0 0 0 0 0x32 R_OFST_I[15:8] R Initial value 0 0 0 0 0 0 0 0 0x33 R_OFST_I[7:0] R Initial value 0 0 0 0 0 0 0 0 0x34 R_OFST_Q[23:16] R Initial value 0 0 0 0 0 0 0 0 0x35 R_OFST_Q[15:8] R Initial value 0 0 0 0 0 0 0 0 0x36 R_OFST_Q[7:0] R Initial value 0 0 0 0 0 0 0 0 R_OFST_I[23:0]: Ich DC Offset Calibration Result (Readback Only) R_OFST_Q[23:0]: Qch DC Offset Calibration Result (Readback Only) DC offset value set by OFST_RSEL[1:0] bits <Address 0x28> are readback. |
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