Datenblatt-Suchmaschine für elektronische Bauteile |
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AK5554VN Datenblatt(PDF) 21 Page - Asahi Kasei Microsystems |
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AK5554VN Datenblatt(HTML) 21 Page - Asahi Kasei Microsystems |
21 / 68 page [AK5554] 015099864-E-00 2016/03 - 21 - (Ta= 40 - +105 C; AVDD= 4.5-5.5 V, TVDD= 1.7-1.98 V (LDOE pin=“L”) or 3.0-3.6 V (LDOE pin=“H”), VDD18= 1.7-1.98 V (LDOE pin=“L”), C L= 10 pF) Parameter Symbol Min. Typ. Max. Unit Audio Interface Timing (Slave mode) (Figure 21) TDM128 mode (TDM1-0 bits = “01”) BICK Period Normal Speed mode Double Speed mode Quad Speed mode BICK Pulse Width Low BICK Pulse Width High LRCK Edge to BICK “↑” (Note 19) BICK “↑” to LRCK Edge (Note 19) BICK “↑” to SDTO1 TDMIN Hold Time TDMIN Setup Time tBCK tBCK tBCK tBCKL tBCKH tLRB tBLR tBSDD tSDH tSDS 1/128fsn 1/128fsd 1/128fsq 14 14 14 14 5 5 5 - - - - - - - - - - - - - - - - - 30 - - ns ns ns ns ns ns ns ns ns ns TDM256 mode (TDM1-0 bits = “10”) BICK Period Normal Speed mode Double Speed mode BICK Pulse Width Low BICK Pulse Width High LRCK Edge to BICK “↑” (Note 19) BICK “↑” to LRCK Edge (Note 19) BICK “↑” to SDTO1 TDMIN Hold Time TDMIN Setup Time tBCK tBCK tBCKL tBCKH tLRB tBLR tBSDD tSDH tSDS 1/256fsn 1/256fsd 14 14 14 14 5 5 5 - - - - - - - - - - - - - - - 30 - - ns ns ns ns ns ns ns ns ns TDM512 mode (TDM1-0 bits = “11”) BICK Period Normal Speed mode BICK Pulse Width Low BICK Pulse Width High LRCK Edge to BICK “↑” (Note 19) BICK “↑” to LRCK Edge (Note 19) BICK “↑” to SDTO1 TDMIN Hold Time TDMIN Setup Time tBCK tBCKL tBCKH tLRB tBLR tBSDD tSDH tSDS 1/512fsn 14 14 14 14 5 5 5 - - - - - - - - - - - - - 30 - - ns ns ns ns ns ns ns ns Note 18. When the 1024fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK5554 should be reset by the PDN pin or RSTN bit. Note 19. BICK rising edge must not occur at the same time as LRCK edge. |
Ähnliche Teilenummer - AK5554VN_16 |
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Ähnliche Beschreibung - AK5554VN_16 |
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