Datenblatt-Suchmaschine für elektronische Bauteile |
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AK5554VN Datenblatt(PDF) 47 Page - Asahi Kasei Microsystems |
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AK5554VN Datenblatt(HTML) 47 Page - Asahi Kasei Microsystems |
47 / 68 page [AK5554] 015099864-E-00 2016/03 - 47 - PW2 pin PW1 pin PW0 pin Power ON/OFF Ch4 Ch3 Ch2 Ch1 L L L OFF OFF OFF OFF L L H ON ON OFF OFF L H L OFF OFF ON ON L H H ON ON ON ON H L L OFF ON ON ON H L H ON ON OFF OFF H H L OFF OFF ON ON H H H ON ON ON ON Table 11. Channel Power ON/OFF (Parallel Control Mode, ODP pin= ”L”) PW2 pin PW1 pin PW0 pin Data on Slot Slot 4 Slot 3 Slot 2 Slot 1 L L L All “0” All “0” All “0” All “0” L L H (CH3+4)/2 (CH3+4)/2 All “0” All “0” L H L All “0” All “0” (CH1+2)/2 (CH1+2)/2 L H H (CH3+4)/2 (CH3+4)/2 (CH1+2)/2 (CH1+2)/2 H L L All “0” CH3 CH2 CH1 H L H CH4 CH3 All “0” All “0” H H L All “0” All “0” CH2 CH1 H H H CH4 CH3 CH2 CH1 Table 12. Slot Data Assign (Parallel Control Mode, ODP pin= “L”) When the ODP pin = “H”, the AK5554 becomes optimal data placement mode and data slots can be used efficiently. The PW2-0 pins control power down, 4-to-2 mode and 4-to-1 mode. In 4-to-2 mode, AIN1 and AIN2 channel data are summed digitally and output from the SDTO1 (DSDOL1) by dividing into half amplitude. In the same manner, AIN3 and AIN4 channel data are summed digitally and output from the SDTO1 (DSDOR2) by dividing into half amplitude. In 4-to-1 mode, AIN1 - AIN4 channel data are summed digitally and output from the SDTO1 (DSDOL1) of the slot1 by dividing into quarter amplitude. PW2 pin PW1 pin PW0 pin Power ON/OFF Ch4 Ch3 Ch2 Ch1 L L L OFF OFF OFF OFF L L H ON ON ON ON L H L ON ON ON ON L H H ON ON ON ON H L L ON ON ON ON H L H ON ON ON ON H H L ON ON ON ON H H H ON ON ON ON Table 13. Channel Power ON/OFF (Parallel Control mode, ODP pin= ”H”) |
Ähnliche Teilenummer - AK5554VN_16 |
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Ähnliche Beschreibung - AK5554VN_16 |
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