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AK5554VN Datenblatt(PDF) 56 Page - Asahi Kasei Microsystems |
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AK5554VN Datenblatt(HTML) 56 Page - Asahi Kasei Microsystems |
56 / 68 page [AK5554] 015099864-E-00 2016/03 - 56 - ■ Operation Mode Control Operation modes of the AK5554 are set by pins or registers. In parallel mode, the operation mode is set by pin and register settings are invalid. Therefore the functions that needs register settings are not available in parallel mode. For register accessing, 3-wire serial and I 2C bus communications are available. This control mode of the AK5554 is selected by the I2C pin and the PSN pin. In serial control mode, register settings are prioritized so that all pin settings except the MSN pin setting are ignored. I2C pin PSN pin Control Mode L L 3-wire Serial L H 3-wire Serial H L I2C Bus H H Parallel Table 22. Control Mode ■ Register Control Interface (1) 3-wire Serial Control mode (I2C pin = “L”) The internal registers may be written through the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this interface consists of a 2- bit Chip address, Read/Write (1bit, Fixed to “1”, Write only), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data are clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For write operations, data is latched after a low-to-high transition of CSN. The clock speed of CCLK is 5MHz (max). The in ternal registers are initialized by setting the PDN pin = “L”. In serial mode, an internal timing circuit is reset by setting RSTN bit = “0” but register values are not initialized. CDTI CCLK C1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D4 D5 D6 D7 A1 A2 A3 A4 R/W C0 A0 D0 D1 D2 D3 CSN C1-C0: Chip Address (C1=CAD1, C0=CAD0) R/W: READ/WRITE (Fixed to “1”, Write only) A4-A0: Register Address D7-D0: Control Data Figure 62. Control I/F Timing * The AK5554 does not support read commands in 3-wire serial control mode. * When the AK5554 is in power down mode (PDN pin = “L”), a writing into the control registers is prohibited. * The control data cannot be written when the CCLK rising edge is 15 times or less, or 17 times or more during CSN is “L”. |
Ähnliche Teilenummer - AK5554VN_16 |
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Ähnliche Beschreibung - AK5554VN_16 |
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