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IIS328DQ Datenblatt(PDF) 28 Page - STMicroelectronics |
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IIS328DQ Datenblatt(HTML) 28 Page - STMicroelectronics |
28 / 40 page Register description IIS328DQ 28/40 DocID027250 Rev 3 The BDU bit is used to inhibit the output register update until both upper and lower register parts are read. In default mode (BDU = ‘0’), the lower and upper register parts are updated continuously. When the BDU is activated (BDU = 1), the content of the output registers is not updated until both MSb and LSb are read which avoids reading values related to different sample times. 7.6 CTRL_REG5 (24h) The TurnOn bits are used for turning on the sleep-to-wake function. By setting TurnOn[1:0] bits to 11, the “sleep-to-wake” function is enabled. When an interrupt event occurs, the device is switched to normal mode, increasing the ODR to the value defined in CTRL_REG1. Although the device is in normal mode, the CTRL_REG1 content is not automatically changed to “normal mode” configuration. 7.7 HP_FILTER_RESET (25h) Dummy register. Reading at this address instantaneously zeroes the content of the internal high-pass filter. If the high-pass filter is enabled, all three axes are instantaneously set to 0 g. This makes it possible to nullify the settling time of the high-pass filter. 7.8 REFERENCE (26h) This register sets the acceleration value taken as a reference for the high-pass filter output. Table 30. CTRL_REG5 register 0 0 0 0 0 0 TurnOn1 TurnOn0 Table 31. CTRL_REG5 description TurnOn1, TurnOn0 Turn-on mode selection for sleep-to-wake function. Default value: 00 Table 32. Sleep-to-wake configuration TurnOn1 TurnOn0 Sleep-to-wake status 0 0 Sleep-to-wake function is disabled 1 1 Turned on: the device is in low-power mode (ODR is defined in CTRL_REG1) Table 33. REFERENCE register Ref7 Ref6 Ref5 Ref4 Ref3 Ref2 Ref1 Ref0 Table 34. REFERENCE description Ref7 - Ref0 Reference value for high-pass filter. Default value: 00h |
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