Product Specification

PE43404

Document No. 70-0258-01 │ www.psemi.com

Page 7 of 11

©2008 Peregrine Semiconductor Corp. All rights reserved.

Programming Options

Parallel/Serial Selection

Either a parallel or serial interface can be used to

control the PE43404. The P/S bit provides this

selection, with P/S=LOW selecting the parallel

interface and P/S=HIGH selecting the serial

interface.

Parallel / Direct Mode Interface

The parallel interface consists of four CMOS-

compatible control lines that select the desired

attenuation state, as shown in Table 5.

The parallel interface timing requirements are

defined by Figure 19 (Parallel Interface Timing

Diagram), Table 9 (Parallel Interface AC

Characteristics), and switching speed (Table 1).

For latched parallel programming, the Latch Enable

(LE) should be held LOW while changing attenuation

state control values, then pulse LE HIGH to LOW

(per Figure 19) to latch new attenuation state into

device.

For direct parallel programming, the Latch Enable

(LE) line should be pulled HIGH. Changing

attenuation state control values will change device

state to new attenuation. Direct Mode is ideal for

manual control of the device (using hardwire,

switches, or jumpers).

Table 5. Truth Table

Serial Interface

The PE43404’s serial interface is a 6-bit serial-in,

parallel-out shift register buffered by a transparent

latch. The latch is controlled by three CMOS-

compatible signals: Data, Clock, and Latch Enable

(LE). The Data and Clock inputs allow data to be

serially entered into the shift register, a process that

is independent of the state of the LE input.

The LE input controls the latch. When LE is HIGH,

the latch is transparent and the contents of the serial

shift register control the attenuator. When LE is

brought LOW, data in the shift register is latched.

The shift register should be loaded while LE is held

LOW to prevent the attenuator value from changing

as data is entered. The LE input should then be

toggled HIGH and brought LOW again, latching the

new data. The start bit (B5) and stop bit (B0) of the

data should always be low to prevent an unknown

state in the device. The timing for this operation is

defined by Figure 18 (Serial Interface Timing

Diagram) and Table 8 (Serial Interface AC

Characteristics).

Power-up Control Settings

The PE43404 always assumes a specifiable

attenuation setting on power-up. This feature exists

for both the Serial and Parallel modes of operation,

and allows a known attenuation state to be

established before an initial serial or parallel control

word is provided.

When the attenuator powers up in Serial mode (P/

S=1), the four control bits are set to whatever data is

present on the four parallel data inputs (C1 to C8).

This allows any one of the 16 attenuation settings to

be specified as the power-up state.

When the attenuator powers up in Parallel mode (P/

S=0) with LE=0, the control bits are automatically set

to one of two possible values. These two values are

selected by the power-up control bit, PUP2, as

shown in Table 6 (Power-Up Truth Table, Parallel

Table 6. Power-Up Truth Table, Parallel

Interface Mode

Note:

Power up with LE=1 provides normal parallel operation

with C1-C8, and PUP2 is not active.

P/S

C8

C4

C2

C1

Attenuation

State

0

0

0

0

0

Reference Loss

0

0

0

0

1

1 dB

0

0

0

1

0

2 dB

0

0

1

0

0

4 dB

0

1

0

0

0

8 dB

0

1

1

1

1

15 dB

Note: Not all 16 possible combinations of C1-C8 are shown in table

P/S

LE

PUP2

Attenuation State

0

0

0

Reference Loss

0

0

1

8 dB

0

1

X

Defined by C1-C8

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