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M41T315Y-85MQ6E Datenblatt(PDF) 8 Page - STMicroelectronics |
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M41T315Y-85MQ6E Datenblatt(HTML) 8 Page - STMicroelectronics |
8 / 24 page M41T315Y*, M41T315V, M41T315W 8/24 Non-volatile Supervisor Operation A switch is provided to direct power from the bat- tery input or VCCI to VCCO with a maximum voltage drop of 0.3 Volts. The VCCO output pin is used to supply uninterrupted power to CMOS SRAM. The M41T315Y/V/W safeguards the clock and RAM data by power-fail detection and write protection. Power-fail detection occurs when VCCI falls below VPFD which is set by an internal bandgap refer- ence. The M41T315Y/V/W constantly monitors the VCCI supply pin. When VCCI is less than VPFD, power-fail circuitry forces the chip enable output (CEO) to VCCI or VBAT-0.2 volts for external RAM write protection. During nominal supply conditions, CEO will track CEI with a propagation delay. Inter- nally, the M41T315Y/V/W aborts any data transfer in progress without changing any of the device registers and prevents future access until VCCI exceeds VPFD. Figure 7., page 6 illustrates a typi- cal RAM/clock interface. Figure 8. READ Mode Waveforms Figure 9. WRITE Mode Waveforms DATA OUTPUT VALID WE CEI OE Q tCW tCO tRC tOW tCOE tODO tRR tOD tOE tOEE AI04259 DATA INPUT STABLE OE D CEI tWP tWC tCW tDH tWR tWR WE t DH tDS AI04261 |
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