TP3069WM datasheet(3/18 Pages) NSC

Teilenummer	TP3069WM

Bauteilbeschribung	Enhanced' Serial Interface CMOS CODEC/Filter COMBO

Download	18 Pages

Scroll/Zoom	100%

Hersteller	NSC [National Semiconductor (TI)]

Direct Link	http://www.national.com

Logo

3 / 18 page

Functional Description

POWER-UP

When power is first applied power-on reset circuitry initializ-

es the COMBOTM and places it into a power-down state All

non-essential circuits are deactivated and the DX VFRO

VPOb and VPOa outputs are put in high impedance states

To power-up the device a logical low level or clock must be

applied to the MCLKR PDN pin and FSX andor FSR pulses

must be present Thus 2 power-down control modes are

available The first is to pull the MCLKR PDN pin high the

alternative is to hold both FSX and FSR inputs continuously

lowthe device will power-down approximately 1 ms after

the last FSX or FSR pulse Power-up will occur on the first

FSX or FSR pulse The TRI-STATE PCM data output DX

will remain in the high impedance state until the second FSX

pulse

SYNCHRONOUS OPERATION

For synchronous operation the same master clock and bit

clock should be used for both the transmit and receive di-

rections In this mode a clock must be applied to MCLKX

and the MCLKR PDN pin can be used as a power-down

control A low level on MCLKR PDN powers up the device

and a high level powers down the device In either case

MCLKX will be selected as the master clock for both the

transmit and receive circuits A bit clock must also be ap-

plied to BCLKX and the BCLKR CLKSEL can be used to

select the proper internal divider for a master clock of

1536 MHz 1544 MHz or 2048 MHz For 1544 MHz opera-

tion the device automatically compensates for the 193rd

clock pulse each frame

With a fixed level on the BCLKR CLKSEL pin BLCKX will be

selected as the bit clock for both the transmit and receive

directions Table I indicates the frequencies of operation

which can be selected depending on the state of BCLKR

CLKSEL In this synchronous mode the bit clock BCLKX

may be from 64 kHz to 2048 MHz but must be synchro-

nous with MCLKX

Each FSX pulse begins the encoding cycle and the PCM

data from the previous encode cycle is shifted out of the

enabled DX output on the positive edge of BCLKX After

8-bit clock periods the TRI-STATE DX output is returned to

a high impedance state With an FSR pulse PCM data is

latched via the DR input on the negative edge of BCLKX (or

BCLKR if running) FSX and FSR must be synchronous with

MCLKXR

TABLE I Selection of Master Clock Frequencies

Master Clock

BCLKR CLKSEL

Frequency Selected

TP3069

Clocked

2048 MHz

0

1536 MHz or 1544 MHz

1

2048 MHz

ASYNCHRONOUS OPERATION

For asynchronous operation separate transmit and receive

clocks may be applied

MCLKX and MCLKR must be

2048 MHz and need not be synchronous For best trans-

mission performance however MCLKR should be synchro-

nous with MCLKX which is easily achieved by applying only

static logic levels to the MCLKR PDN pin This will automati-

cally connect MCLKX to all internal MCLKR functions (see

Pin Description) For 1544 MHz operation the device auto-

matically compensates for the 193rd clock pulse each

frame FSX starts each encoding cycle and must be syn-

chronous with MCLKX and BCLKX FSR starts each decod-

ing cycle and must be synchronous with BCLKR BCLKR

must be a clock the logic levels shown in Table I are not

valid in asynchronous mode BCLKX and BCLKR may oper-

ate from 64 kHz to 2048 MHz

SHORT FRAME SYNC OPERATION

The COMBO can utilize either a short frame sync pulse or a

long frame sync pulse Upon power initialization the device

assumes a short frame mode In this mode both frame sync

pulses FSX and FSR must be one bit clock period long

with timing relationships specified in

Figure 2 With FSX high

during a falling edge of BCLKX the next rising edge of

BCLKX enables the DX TRI-STATE output buffer which will

output the sign bit The following seven rising edges clock

out the remaining seven bits and the next falling edge dis-

ables the DX output With FSR high during a falling edge of

BCLKR (BCLKX in synchronous mode) the next falling edge

of BCLKR latches in the sign bit The following seven falling

edges latch in the seven remaining bits All devices may

utilize the short frame sync pulse in synchronous or asyn-

chronous operating mode

LONG FRAME SYNC OPERATION

To use the long frame mode both the frame sync pulses

FSX and FSR must be three or more bit clock periods long

with timing relationships specified in

Figure 3 Based on the

transmit frame sync FSX the COMBO will sense whether

short or long frame sync pulses are being used For 64 kHz

operation the frame sync pulse must be kept low for a mini-

mum of 160 ns The DX TRI-STATE output buffer is enabled

with the rising edge of FSX or the rising edge of BCLKX

whichever comes later and the first bit clocked out is the

sign bit The following seven BCLKX rising edges clock out

the remaining seven bits The DX output is disabled by the

falling BCLKX edge following the eighth rising edge or by

FSX going low whichever comes later A rising edge on the

receive frame sync pulse FSR will cause the PCM data at

DR to be latched in on the next eight falling edges of

BCLKR(BCLKX in synchronous mode) All devices may uti-

lize the long frame sync pulse in synchronous or asynchro-

nous mode

TRANSMIT SECTION

The transmit section input is an operational amplifier with

provision for gain adjustment using two external resistors

see

Figure 4 The low noise and wide bandwidth allow gains

in excess of 20 dB across the audio passband to be real-

ized The op amp drives a unity-gain filter consisting of RC

active pre-filter followed by an eighth order switched-ca-

pacitor bandpass filter clocked at 256 kHz The output of

this filter directly drives the encoder sample-and-hold circuit

The AD is of companding type according to A-law coding

conventions A precision voltage reference is trimmed in

manufacturing to provide an input overload (tMAX) of nomi-

nally 25V peak (see table of Transmission Characteristics)

3

TP3069WM Datenblatt(PDF) 3 Page - National Semiconductor (TI)

TP3069WM Datenblatt(HTML) 3 Page - National Semiconductor (TI)

Ähnliche Teilenummer - TP3069WM

Ähnliche Beschreibung - TP3069WM

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Datenblatt Download

Link URL