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TP3420AV Datenblatt(PDF) 2 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Teilenummer TP3420AV
Bauteilbeschribung  ISDN S/T Interface Device
Download  32 Pages
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Hersteller  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

TP3420AV Datenblatt(HTML) 2 Page - National Semiconductor (TI)

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Block Diagram
Connection Diagrams
Pin Descriptions
Name
Description
GND
Negative power supply pin, normally 0V
(ground). All analog and digital signals
are referenced to this pin.
V
CC
Positive power supply input, which must
be +5V ±5% relative to GND.
MCLK/XTAL
The 15.36 MHz Master Clock input, which
requires either a crystal (Note 1) to be
tied between this pin and XTAL2, or a
CMOS logic level clock input from a
stable source. When using a crystal, a
total of 33 pF load capacitance to GND
must also be connected. (Note 2)
XTAL2
The output of the crystal oscillator, which
should be connected to one end of the
crystal, and 33 pF of load capacitance to
GND. (Note 2) If using an external master
Clock via the MCLK pin, leave the XTAL2
pin unconnected.
BCLK
The Bit Clock pin, which determines the
data shift rate for “B” and “D” channel
data at the digital interface. When NT
mode or TES mode is selected, BCLK is
a TTL/CMOS input which may be any
multiple of 8 kHz from 256 kHz to 4.096
MHz. It need not be synchronous with
MCLK.
When TEM mode is selected, this pin is a
CMOS output at frequency selected by
the Digital Interface Format. This clock is
phase-locked to the received line signal
and is synchronous with the data on B
x
and B
r.
DS009143-1
TP3420A SID
DS009143-20
Order Number TP3420AV
See NS Package Number V20A
TP3420A SID
DS009143-2
Top View
Order Number TP3420AJ or TP3420AN
See NS Package Number J20A or N20A
www.national.com
2


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