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RX113 Datenblatt(PDF) 85 Page - Renesas Technology Corp

Teilenummer RX113
Bauteilbeschribung  32 MHz, 32-bit RX MCUs, 50 DMIPS, up to 512 Kbytes of flash memory
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RX113 Datenblatt(HTML) 85 Page - Renesas Technology Corp

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R01DS0216EJ0110 Rev.1.10
Page 85 of 131
Mar 31, 2016
RX113 Group
5. Electrical Characteristics
Note 1. tPcyc: PCLK cycle
Note 2. N: An integer from 1 to 8 that can be set by the RSPI clock delay register (SPCKD)
Note 3. N: An integer from 1 to 8 that can be set by the RSPI slave select negation delay register (SSLND)
Table 5.31
Timing of On-Chip Peripheral Modules (2)
Conditions: 1.8 V
≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V,
Ta = –40 to +105°C, C = 30 pF
Item
Symbol
Min.
Max.
Unit
Test
Conditions
RSPI
RSPCK clock cycle
Master
tSPcyc
2
4096
tPcyc*1 Figure 5.42
Slave
8
4096
RSPCK clock
high pulse width
Master
tSPCKWH (tSPcyc – tSPCKr
tSPCKf)/2 – 3
—ns
Slave
(tSPcyc – tSPCKr
tSPCKf)/2
RSPCK clock
low pulse width
Master
tSPCKWL
(tSPcyc – tSPCKr
tSPCKf)/2 – 3
—ns
Slave
(tSPcyc – tSPCKr
tSPCKf)/2
RSPCK clock
rise/fall time
Output
2.7 V or above
tSPCKr,
tSPCKf
—10
ns
1.8 V or above
—15
Input
—1
μs
Data input setup time
Master
2.7 V or above
tSU
10
ns
Figure 5.43
to
Figure 5.48
1.8 V or above
30
Slave
25 – tPcyc
Data input hold time
Master
RSPCK set to a division
ratio other than PCLKB
divided by 2
tH
tPcyc
—ns
RSPCK set to PCLKB
divided by 2
tHF
0—
Slave
tH
20 + 2 × tPcyc
SSL setup time
Master
tLEAD
–30 + N*2 ×
tSPcyc
—ns
Slave
2—
tPcyc
SSL hold time
Master
tLAG
–30 + N*3 ×
tSPcyc
—ns
Slave
2—
tPcyc
Data output delay time
Master
2.7 V or above
tOD
—14
ns
1.8 V or above
—30
Slave
2.7 V or above
—3 × tPcyc + 65
1.8 V or above
—3 × tPcyc +105
Data output hold time
Master
2.7 V or above
tOH
0—
ns
1.8 V or above
–20
Slave
0—
Successive
transmission delay
time
Master
tTD
tSPcyc + 2 × tPcyc
8 × tSPcyc + 2 ×
tPcyc
ns
Slave
4 × tPcyc
MOSI and MISO rise/
fall time
Output
2.7 V or above
tDr, tDf
—10
ns
1.8 V or above
—20
Input
—1
μs
SSL rise/fall time
Output
tSSLr,
tSSLf
—20
ns
Input
—1
μs
Slave access time
2.7 V or above
tSA
—6
tPcyc
Figure 5.47,
Figure 5.48
1.8 V or above
—7
Slave output release time
2.7 V or above
tREL
—5
tPcyc
1.8 V or above
—6


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