Datenblatt-Suchmaschine für elektronische Bauteile |
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S5D9 Datenblatt(PDF) 68 Page - Renesas Technology Corp |
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S5D9 Datenblatt(HTML) 68 Page - Renesas Technology Corp |
68 / 115 page R01DS0303EU0100 Rev.1.00 Page 68 of 115 Nov 3, 2016 S5D9 2. Electrical Characteristics 2.3.11 SPI Timing Note 1. tPcyc: PCLKA cycle. Table 2.25 SPI timing Conditions: For RSPCKA and RSPCKB pins, high drive output is selected with the port drive capability bit in the PmnPFS register. For other pins, middle drive output is selected in the port drive capability bit in the PmnPFS register. Item Symbol Min Max Unit*1 Test conditions*2 SPI RSPCK clock cycle Master tSPcyc 2 (PCLKA 60 MHz) 4 (PCLKA > 60 MHz) 4096 tPcyc Figure 2.47 C = 30 pF Slave 4 4096 RSPCK clock high pulse width Master tSPCKWH (tSPcyc – tSPCKR – tSPCKF) / 2 – 3 -ns Slave 2 × tPcyc - RSPCK clock low pulse width Master tSPCKWL (tSPcyc – tSPCKR – tSPCKF) / 2 – 3 -ns Slave 2 × tPcyc - RSPCK clock rise and fall time Master tSPCKr, tSPCKf -5 ns Slave - 1 µs Data input setup time Master tSU 4- ns Figure 2.48 to Figure 2.53 C = 30 pF Slave 5 - Data input hold time Master (PCLKA division ratio set to 1/2) tHF 0- ns Master (PCLKA division ratio set to a value other than 1/2) tH tPcyc - Slave tH 20 - SSL setup time Master tLEAD N × tSPcyc - 10*3 N × tSPcyc + 100*3 ns Slave 6 x tPcyc -ns SSL hold time Master tLAG N × tSPcyc - 10 *4 N × tSPcyc + 100*4 ns Slave 6 x tPcyc -ns Data output delay Master tOD -6.3 ns Slave - 20 Data output hold time Master tOH 0- ns Slave 0 - Successive transmission delay Master tTD tSPcyc + 2 × tPcyc 8 × tSPcyc + 2 × tPcyc ns Slave 6 × tPcyc MOSI and MISO rise and fall time Output tDr, tDf -5 ns Input - 1 μs SSL rise and fall time Output tSSLr, tSSLf -5 ns Input - 1 μs Slave access time tSA -2 x tPcyc + 28 ns Figure 2.52 and Figure 2.53 C = 30PF Slave output release time tREL -2 x tPcyc + 28 |
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