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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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S7G2 Datenblatt(PDF) 2 Page - Renesas Technology Corp |
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S7G2 Datenblatt(HTML) 2 Page - Renesas Technology Corp |
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2 / 116 page  R01DS0262EU0100 Rev.1.00 Page 2 of 113 Feb 23, 2016 S7G2 1. Overview 1. Overview The S7G2 MCU integrates multiple series of software- and pin-compatible ARM®-based 32-bit MCUs that share the same set of Renesas peripherals to facilitate design scalability and efficient platform-based product development. The MCU provides a high-performance ARM Cortex®-M4 core running up to 240 MHz with the following features: Up to 4-MB code flash memory 640-KB SRAM Graphics LCD Controller (GLCDC) 2D Drawing Engine (DRW) Capacitive Touch Sensing Unit (CTSU) Ethernet MAC Controller (ETHERC) with IEEE 1588 PTP, USBFS, USBHS, SD/MMC Host Interface Quad Serial Peripheral Interface (QSPI) Security and safety features Analog peripherals. 1.1 Function Outline Table 1.1 ARM core Feature Functional description ARM Cortex-M4 Maximum operating frequency: up to 240 MHz ARM Cortex-M4 core: - Revision: r0p1-01rel0 - ARMv7E-M architecture profile - Single precision floating point unit compliant with the ANSI/IEEE Std 754-2008 ARM Memory Protection Unit (MPU): - ARMv7 Protected Memory System Architecture - 8 protect regions SysTick timer: - Driven by LOCO clock Table 1.2 Memory Feature Functional description Code flash memory Maximum 4 MB of code flash memory. See section 54, Flash Memory in User's Manual. Data flash memory 64 KB of data flash memory. See section 54, Flash Memory in User's Manual. Memory Mirror Function (MMF) The MMF can be configured to mirror the wanted application image load address in code flash memory to the application image link address in the 23-bit unused memory space (memory mirror space addresses). Your application code is developed and linked to run from this MMF destination address. The application code does not need to know the load location where it is stored in code flash memory. See section 5, Memory Mirror Function (MMF) in User's Manual. SRAM On-chip high-speed SRAM providing either parity-bit or double-bit error detection (DED). The first 32 KB of SRAM0 is subject to DED. Parity check is performed for other areas. See section 52, SRAM in User's Manual. Standby SRAM On-chip SRAM that can retain data in Deep Software Standby mode. See section 53, Standby SRAM in User's Manual. Table 1.3 System (1/2) Feature Functional description Operating modes Two operating modes: - Single-chip mode - SCI or USB boot mode. See section 3, Operating Modes in User's Manual. |
Ähnliche Beschreibung - S7G2 |
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