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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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UPD48288209AF1 Datenblatt(PDF) 20 Page - Renesas Technology Corp |
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UPD48288209AF1 Datenblatt(HTML) 20 Page - Renesas Technology Corp |
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20 / 54 page  µµµµPD48288209AF1, µµµµPD48288218AF1, µµµµPD48288236AF1 R10DS0254EJ0101 Rev. 1.01 Page 20 of 53 Jan. 15, 2016 Figure 2-2. Clock Input Notes 1. DKx and DKx# have the same requirements as CK and CK#. 2. All voltages referenced to VSS. 3. Tests for AC timing, IDD and electrical AC and DC characteristics may be conducted at normal reference/supply voltage levels; but the related specifications and device operations are tested for the full voltage range specified. 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or the crossing point for CK/CK#), and parameters specifications are tested for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 2V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the HSTL Standard (i.e. the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above[below] the DC input LOW[HIGH] level). 6. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross. The input reference level for signal other than CK/CK# is VREF. 7. CK and CK# input slew rate must be >= 2V/ns (>=4V/ns if measured differentially). 8. VID is the magnitude of the difference between the input level on CK and input level on CK#. 9. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same. 10. CK and CK# must cross within the region. 11. CK and CK# must meet at least VID(DC) (MIN.) when static and centered around VDDQ/2. 12. Minimum peak-to-peak swing. VIN(DC) MAX. CK# VDD Q/2 + 0.15 VDD Q/2 VDD Q/2 - 0.15 CK VIN(DC) MIN. Minimum Clock Level VIX(AC) MAX. VIX(AC) MIN. VID(DC) Note11 VID(AC) Note12 Note 10 Maximum Clock Level |
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Ähnliche Beschreibung - UPD48288209AF1 |
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