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UPD48576209F1 Datenblatt(PDF) 23 Page - Renesas Technology Corp

Teilenummer UPD48576209F1
Bauteilbeschribung  576M-BIT Low Latency DRAM
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD48576209F1 Datenblatt(HTML) 23 Page - Renesas Technology Corp

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R10DS0256EJ0101 Rev. 1.01
Page 23 of 53
Jan. 15, 2016
2.10 Write Operation (WRITE)
Write accesses are initiated with a WRITE command, as shown in Figure 2-6. Row and bank addresses are provided
together with the WRITE command. During WRITE commands, data will be registered at both edges of DK according
to the programmed burst length (BL). A WRITE latency (WL) one cycle longer than the programmed READ latency (RL
+ 1) is present, with the first valid data registered at the first rising DK edge WL cycles after the WRITE command.
Any WRITE burst may be followed by a subsequent READ command. Figure 2-10. WRITE Followed By READ: BL=2,
RL=4, WL=5, Configuration 1
and Figure 2-11. WRITE Followed By READ: BL=4, RL=4, WL=5, Configuration 1
illustrate the timing requirements for a WRITE followed by a READ for bursts of two and four, respectively.
Setup and hold times for incoming input data relative to the DK edges are specified as tDS and tDH. The input data is
masked if the corresponding DM signal is HIGH. The setup and hold times for data mask are also tDS and tDH.
Figure 2-6. WRITE Command
Remark
A : Address
BA: Bank address
Figure 2-7. Basic WRITE Burst / DM Timing
CK#
CK
WE#
REF#
CS#
ADDRESS
BANK
ADDRESS
A
BA
Don't care
DQ
DM
tDH
tDS
D0
D3
DKx#
DKx
tDH
tDS
tDH
tDS
Don't care
Write
Latency
Data
masked
Data
masked
CK#
CK
tCKDK
D1
D2


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