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HT82A525R Datenblatt(PDF) 23 Page - Holtek Semiconductor Inc

Teilenummer HT82A525R
Bauteilbeschribung  I/O Type USB 8-Bit OTP MCU with SPI
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Hersteller  HOLTEK [Holtek Semiconductor Inc]
Direct Link  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT82A525R Datenblatt(HTML) 23 Page - Holtek Semiconductor Inc

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low level to RES), software instructions, or a
²HALT² instruction. The software instructions include
²CLR WDT² and the other set -- ²CLR WDT1² and ²CLR WDT2². Of these two types of instruction,
only one can be active depending on the option --
²CLR WDT² times selection option. If the ²CLR WDT²
is selected (i.e. CLR WDT times equal one), any execution of the
²CLR WDT² instruction will clear the
WDT. In case
²CLR WDT1² and ²CLR WDT2² are chosen (i.e. ²CLRWDT² times equal two), these two
instructions must be executed to clear the WDT, otherwise, the WDT may reset the chip due to time-out.
There are two
²Timer out WDT clear² modes selected by configuration option. One is ²Half WDT clear²
and the other is
²Full WDT scale².The ²Half WDT clear² is only to clear the highest two bits of WDT
counter and the
²Full WDT clear² is to clear all bits of WDT counter.
Power Down Operation
- HALT
The HALT mode is initialized by the
²HALT² instruction and results in the following:
· The system oscillator is turned off but the WDT oscillator keeps running (if the WDT oscillator is
selected).
· The contents of the on-chip RAM and registers remain unchanged.
· The WDT will be cleared and start recounting (if the WDT clock source is from the WDT oscillator).
· All of the I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
The system can quit the HALT mode in many ways, by an external reset, an interrupt (except serial in-
terface interrupt and serial interface 2 interrupt), an external falling edge signal on I/O ports or a WDT
overflow. An external reset causes a device initialization and the WDT overflow performs a
²warm re-
set
². After examining the TO and PDF flags, the cause for a chip reset can be determined. The PDF flag
is cleared by a system power-up or by executing the
²CLR WDT² instruction and is set when executing
the
²HALT² instruction. On the other hand, the TO flag is set if the WDT time-out occurs, and causes a
wake-up that only resets the Program Counter and Stack Pointer; and leaves the others in their original
status.
The Port A wake-up and interrupt methods can be considered as a continuation of normal execution.
Each bit in Port A can be independently selected to wake-up the device by option. Awakening from an
I/O port stimulus, the program will resume execution of the next instruction. If it awakens from an
interrupt, two sequences may occur. If the related interrupt is disabled or the interrupt is enabled but
the stack is full, the program will resume execution at the next instruction. But if the interrupt is
enabled and the stack is not full, a regular interrupt response takes place. When an interrupt request
flag is set to
²1² before entering the HALT mode, the wake-up function of the related interrupt will be
disabled. If a wake-up event occurs, it takes 1024 fSYS (system clock period) to resume normal
operation. In other words, a dummy period is inserted after wake-up. If the wake-up results from an
interrupt acknowledge, the actual interrupt subroutine execution is delayed by more than one cycle.
Rev. 1.80
23
March 11, 2016
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
f W D T / 2 8
S y s t e m C l o c k / 4
D i v i d e r
W D T P r e s c a l e r
M a s k O p t i o n
C o n f i g u r a t i o n
O p t i o n
W D T O S C
( 1 2 k H z )
f W D T
C K
R
T
C K
R
T
H a l f W D T C l e a r
T i m e r - o u t R e s e t
H a l f W D T C l e a r
2
~ 2
/ f s
2
~ 2
/ f s
2
~ 2
/ f s
2
~ 2
/ f s
1 2
1 3
1 4
1 5
1 3
1 4
1 5
1 6
F u l l W D T C l e a r
2
/ f S
2
/ f S
2
/ f S
2
/ f S
1 6
1 5
1 4
1 3
F u l l W D T C l e a r
N o t e : f S = f W D T
Watchdog Timer


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