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AD5252BRU50 Datenblatt(PDF) 9 Page - Analog Devices |
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AD5252BRU50 Datenblatt(HTML) 9 Page - Analog Devices |
9 / 28 page AD5251/AD5252 Rev. 0 | Page 9 of 28 PIN CONFIGURATION AND FUNCTION DESCRIPTION 1 2 3 4 5 6 7 AD0 WP W1 SDA A1 B1 VDD 14 13 12 11 10 9 8 B3 A3 AD1 VSS SCL DGND W3 AD5251/ AD5252 TOP VIEW (Not to Scale) Figure 2. AD5251/AD5252 in TSSOP-14 Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 VDD Positive Power Supply Pin. Connect +2.7 V to +5 V for single supply or ±2.7 V for dual supply, where VDD – VSS ≤ 5.5 V. VDD must be able to source 35 mA for 26 ms when storing data to EEMEM. 2 AD0 I2C Device Address 0. AD0 and AD1 allow four AD5251/AD5252s to be addressed. 3 WP Write Protect, Active Low. VWP ≤ VDD + 0.3 V. 4 W1 Wiper Terminal of RDAC1. VSS ≤ VW1 ≤ VDD.1 5 B1 B Terminal of RDAC1. VSS ≤ VB1 ≤ VDD.1 6 A1 A Terminal of RDAC1. VSS ≤ VA1 ≤ VDD.1 7 SDA Serial Data Input/Output Pin. Shifts in one bit at a time on positive clock edges. MSB loaded first. Open-drain MOSFET requires pull-up resistor. 8 VSS Negative Supply. Connect to 0 V for single supply or –2.7 V for dual supply, where VDD – VSS ≤ +5.5 V. If VSS is used, other than grounded, in dual supply, VSS must be able to sink 35 mA for 26 ms when storing data to EEMEM. 9 SCL Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges. VSCL ≤ (VDD + 0.3 V). Pull-up resistor is recommended for SCL to ensure minimum power. 10 DGND Digital Ground. Connect to system analog ground at a single point. 11 AD1 I2C Device Address 1. AD0 and AD1 allow four AD5251/AD5252s to be addressed. 12 A3 A Terminal of RDAC3. VSS ≤ VA3 ≤ VDD.1 13 B3 B Terminal of RDAC3. VSS ≤ VB3 ≤ VDD.1 14 W3 W Terminal of RDAC3. VSS ≤ VW3 ≤ VDD.1 1 For quad-channel device software compatibility, the dual potentiometers in the parts are designated as RDAC1 and RDAC3. I2C INTERFACE TIMING DIAGRAM t1 SCL SDA PS P t3 t2 t8 t9 t8 t9 t4 t5 t7 t6 t10 Figure 3. I2C Timing Diagram |
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