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MT9V024 Datenblatt(PDF) 7 Page - ON Semiconductor

Teilenummer MT9V024
Bauteilbeschribung  1/3-Inch Wide VGA CMOS Digital Image Sensor
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MT9V024 Datenblatt(HTML) 7 Page - ON Semiconductor

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COLOR (RGB BAYER) DEVICE LIMITATIONS
The color version of the MT9V024 does not support or
offers
reduced
performance
for
the
following
functionalities.
Pixel Binning
Pixel binning is done on immediate neighbor pixels only,
no facility is provided to skip pixels according to a Bayer
pattern. Therefore, the result of binning combines pixels of
different colors. See “Pixel Binning” for additional
information.
Interlaced Readout
Interlaced readout yields one field consisting only of red
and green pixels and another consisting only of blue and
green pixels. This is due to the Bayer pattern of the CFA.
Automatic Black Level Calibration
When the color bit is set (R0x0F[1]=1), the sensor uses
black level correction values from one green plane, which
are applied to all colors. To use the calibration value based
on all dark pixels’ offset values, the color bit should be
cleared.
Defective Pixel Correction
For defective pixel correction to calculate replacement
pixel values correctly, for color sensors the color bit must be
set (R0x0F[1] = 1). However, the color bit also applies
unequal offset to the color planes, and the results might not
be acceptable for some applications.
Other Limiting Factors
Black level correction and row−wise noise correction are
applied uniformly to each color. The row−wise noise
correction algorithm does not work well in color sensors.
Automatic exposure and gain control calculations are made
based on all three colors, not just the green channel. High
dynamic range does operate in color; however,
ON Semiconductor strongly recommends limiting use to
linear operation where good color fidelity is required.
OUTPUT DATA FORMAT
The MT9V024 image data can be read out in a progressive
scan or interlaced scan mode. Valid image data is surrounded
by horizontal and vertical blanking, as shown in Figure 7.
The amount of horizontal and vertical blanking is
programmable through R0x05 and R0x06, respectively
(R0xCD and R0xCE for context B). LV is HIGH during the
shaded region of the figure. See “Output Data Timing” for
the description of FV timing.
VALID iMAGE
HORIZONTAL
BLANKING
VERTICAL/HORIZONTAL
BLANKING
VERTICAL BLANKING
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
P0,0 P0,1 P0,2…………P0,n−1 P0,n
P1,0 P1,1 P1,2…………P1,n−1 P1,n
Pm−1,0 Pm−1,1…………Pm−1,n−1 Pm−1,n
Pm,0 Pm,1…………Pm,n−1 Pm,n
Figure 7. Spatial Illustration of Image Readout
Output Data Timing
The data output of the MT9V024 is synchronized with the
PIXCLK output. When LINE_VALID (LV) is HIGH, one
10−bit pixel datum is output every PIXCLK period.


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