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MT9V032 Datenblatt(PDF) 46 Page - ON Semiconductor

Teilenummer MT9V032
Bauteilbeschribung  1/3?륤nch Wide VGA CMOS Digital Image Sensor
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Hersteller  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MT9V032 Datenblatt(HTML) 46 Page - ON Semiconductor

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MT9V032
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Row10
(9:0)
Row4
(9:0)
Row5
(9:0)
Row6
(9:0)
Row7
(9:0)
Row8
7(9:0)
Row9
(9:0)
LINE_VALID
Normal readout
LINE_VALID
Row Bin 2 readout
LINE_VALID
Row Bin 4 readout
Row11
(9:0)
Row4
(9:0)
Row6
(9:0)
Row8
(9:0)
Row10
(9:0)
Row4
(9:0)
Row8
(9:0)
Figure 30. Readout of 8 Pixels in Normal and Row bin Output Mode
DOUT(9:0)
DOUT(9:0)
DOUT(9:0)
Column Binning
In setting bit 2 or 3 of R0x0D, the pixel data rate is slowed
down by a factor of either two or four, respectively. This is
due to the overhead time in the digital pixel data processing
chain. As a result, the pixel clock speed is also reduced
accordingly.
Figure 31. Readout of 8 Pixels in Normal and Column Bin Output Mode
d1234
(9:0)
LINE_VALID
Normal readout
DOUT(9:0
)
PIXCLK
LINE_VALID
Column Bin 2 readout
DOUT(9:0
)
PIXCLK
LINE_VALID
Column Bin 4 readout
DOUT(9:0
)
PIXCLK
D1
(9:0)
D3
(9:0)
D4
(9:0)
D5
(9:0)
D6
(9:0)
D7
(9:0)
D2
(9:0)
D8
(9:0)
D12
(9:0)
D34
(9:0)
D56
(9:0)
D78
(9:0)
d5678
(9:0)
DOUT(9:0)
DOUT(9:0)
DOUT(9:0)
Interlaced Readout
The MT9V032 has two interlaced readout options. By
setting R0x07[2:0] = 1, all the even−numbered rows are read
out first, followed by a number of programmable field
blanking (R0xBF, bits 7:0), and then the odd−numbered
rows and finally vertical blanking (minimum is 4 blanking
rows). By setting R0x07[2:0] = 2, only one field is read out;
consequently, the number of rows read out is half what is set
in R0x03. The row start address (R0x02) determines which
field gets read out; if the row start address is even, the even
field is read out; if row start address is odd, the odd field is
read out.


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