Datenblatt-Suchmaschine für elektronische Bauteile |
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MT9V032 Datenblatt(PDF) 28 Page - ON Semiconductor |
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MT9V032 Datenblatt(HTML) 28 Page - ON Semiconductor |
28 / 61 page MT9V032 www.onsemi.com 28 Table 8. REGISTER DESCRIPTIONS 0XAB (171) AGC LOW PASS FILTER 1:0 Gain LPF This value plays a role in determining the increment/decre- ment size of gain value from frame to frame. If current bin ! 0 (R0xBC) When Gain LPF = 0 Actual new gain = Calculated new gain When Exp LPF = 1 if |(Calculated new gain − current gain) | > (current gain/4), Actual new gain = Calculated new gain, otherwise Actual new gain = Current exp+ (calculated new gain/2) When Exp LPF = 2: if |(Calculated new gain − current gain) | > (current gain /4), Actual new gain = Calculated new gain, otherwise Actual new gain = Current gain+ (calculated new gain/4). 2 Y 0–2 W 0XAF (175) AGC/AEC ENABLE 0 AEC Enable 0 = Disable Automatic Exposure Control 1 = Enable Automatic Exposure Control 1 Y 0, 1 W 1 AGC Enable 0 = Disable Automatic Gain Control. 1 = Enable Automatic Gain Control. 1 Y 0, 1 W 0XB0 (176) AGC/AEC PIXEL COUNT 15−0 Pixel Count The number of pixel used for the AEC/AGC histogram. ABE0 (44,00) Y 0–65535 W 0XB1 (177) LVDS MASTER CONTROL 0 PLL Bypass 0 = Internal shift−CLK is driven by PLL. 1 = Internal shift−CLK is sourced from the LVDS_BY- PASS_CLK. 0 Y 0, 1 W 1 LVDS Power−down 0 = Normal operation. 1 = Power−down LVDS block. 1 Y 0, 1 W 2 PLL Test Mode 0 = Normal operation. 1 = The PLL output frequency is equal to the system clock frequency (26.6 MHz). 0 Y 0, 1 W 3 LVDS Test Mode 0 = Normal operation. 1 = The SER_DATAOUT_P drives a square wave in both stereo and stand−alone modes). In stereo mode, ensure that SER_DATAIN_P is logic “0.” 0 Y 0, 1 W 0XB2 (178) LVDS SHIFT CLOCK CONTROL 2:0 Shift−clk Delay Element Select The amount of shift−CLK delay that minimizes inter−sensor skew. 0 Y 0–7 W 4 LVDS Receiver Power− down When set, LVDS receiver is disabled. 1 Y 0, 1 W 0XB3 (179) LVDS DATA CONTROL 2:0 Data Delay Element Select The amount of data delay that minimizes inter−sensor skew. 0 Y 0–7 W 4 LVDS Driver Power− down When set, data LVDS driver is disabled. 1 Y 0, 1 W 0XB4 (180) LVDS LATENCY 1:0 Stream Latency Select The amount of delay so that the two streams are in sync. 0 Y 0–3 W 0XB5 (181) LVDS INTERNAL SYNC 0 LVDS Internal Sync En- able When set, the MT9V032 generates sync pattern (data with all zeros except start bit) on LVDS_SER_DATA_OUT. 0 Y 0, 1 W 0XB6 (182) LVDS PAYLOAD CONTROL |
Ähnliche Teilenummer - MT9V032_17 |
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Ähnliche Beschreibung - MT9V032_17 |
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