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AD9925BBCZRL Datenblatt(PDF) 7 Page - Analog Devices

Teilenummer AD9925BBCZRL
Bauteilbeschribung  CCD Signal Processor with Vertical Driver and Precision Timing Generator
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Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

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AD9925
Rev. A | Page 7 of 96
TIMING SPECIFICATIONS
CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, fCLI = 36 MHz, unless otherwise noted.
Table 5.
Parameter
Symbol
Min
Typ
Max
Unit
MASTER CLOCK, CLI (Figure 17)
CLI Clock Period
tCONV
27.8
ns
CLI High/Low Pulse Width
11.2
13.9
16.6
ns
Delay from CLI Rising Edge to Internal Pixel Position 0
tCLIDLY
6
ns
AFE CLPOB PULSE WIDTH1, 2 (Figure 23 and Figure 29)
2
20
Pixels
AFE SAMPLE LOCATION1 (Figure 20)
SHP Sample Edge to SHD Sample Edge
tS1
12.5
13.9
ns
DATA OUTPUTS (Figure 21 and Figure 22)
Output Delay from DCLK Rising Edge, Default Value1
tOD
8
ns
Inhibited Area for DOUTPHASE Edge Location1
tDOUTINH
SHDLOC
SHDLOC + 11
Pipeline Delay from SHP/SHD Sampling to DOUT
11
Cycles
SERIAL INTERFACE (Figure 74 and Figure 75)
Maximum SCK Frequency
fSCLK
36
MHz
SL to SCK Setup Time
tLS
10
ns
SCK to SL Hold Time
tLH
10
ns
SDATA Valid to SCK Rising Edge Setup
tDS
10
ns
SCK Falling Edge to SDATA Valid Hold
tDH
10
ns
SCK Falling Edge to SDATA Valid Read
tDV
10
ns
1 Parameter is register-programmable.
2 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.


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