Datenblatt-Suchmaschine für elektronische Bauteile |
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M41ST87YMX6 Datenblatt(PDF) 10 Page - STMicroelectronics |
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M41ST87YMX6 Datenblatt(HTML) 10 Page - STMicroelectronics |
10 / 42 page M41ST87Y, M41ST87W 10/42 Data Valid. The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowl- edges with a ninth bit. By definition a device that gives out a message is called “transmitter,” the receiving device that gets the message is called “receiver.” The device that controls the message is called “master.” The de- vices that are controlled by the master are called “slaves.” Acknowledge. Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge relat- ed clock pulse. A slave receiver which is ad- dressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low dur- ing the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must sig- nal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line High to enable the master to generate the STOP condition. Figure 6. Serial Bus Data Transfer Sequence Figure 7. Acknowledgement Sequence AI00587 DATA CLOCK DATA LINE STABLE DATA VALID START CONDITION CHANGE OF DATA ALLOWED STOP CONDITION AI00601 DATA OUTPUT BY RECEIVER DATA OUTPUT BY TRANSMITTER SCL FROM MASTER START CLOCK PULSE FOR ACKNOWLEDGEMENT 12 89 MSB LSB |
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