Datenblatt-Suchmaschine für elektronische Bauteile
  German  ▼
ALLDATASHEETDE.COM

X  

AD9243EB Datenblatt(PDF) 9 Page - Analog Devices

Teilenummer AD9243EB
Bauteilbeschribung  Complete 14-Bit, 3.0 MSPS Complete 14-Bit, 3.0 MSPS
Download  25 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9243EB Datenblatt(HTML) 9 Page - Analog Devices

Back Button AD9243EB Datasheet HTML 5Page - Analog Devices AD9243EB Datasheet HTML 6Page - Analog Devices AD9243EB Datasheet HTML 7Page - Analog Devices AD9243EB Datasheet HTML 8Page - Analog Devices AD9243EB Datasheet HTML 9Page - Analog Devices AD9243EB Datasheet HTML 10Page - Analog Devices AD9243EB Datasheet HTML 11Page - Analog Devices AD9243EB Datasheet HTML 12Page - Analog Devices AD9243EB Datasheet HTML 13Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 25 page
background image
AD9243
REV. A
–8–
Therefore, the equation,
VCORE = VINA – VINB
(1)
defines the output of the differential input stage and provides the
input to the A/D core.
The voltage, VCORE, must satisfy the condition,
–VREF
≤ V
CORE
≤ VREF
(2)
where VREF is the voltage at the VREF pin.
While an infinite combination of VINA and VINB inputs exist
that satisfy Equation 2, there is an additional limitation placed
on the inputs by the power supply voltages of the AD9243. The
power supplies bound the valid operating range for VINA and
VINB. The condition,
AVSS – 0.3 V < VINA < AVDD + 0.3 V
(3)
AVSS – 0.3 V < VINB < AVDD + 0.3 V
where AVSS is nominally 0 V and AVDD is nominally +5 V,
defines this requirement. Thus, the range of valid inputs for
VINA and VINB is any combination that satisfies both Equa-
tions 2 and 3.
For additional information showing the relationship between
VINA, VINB, VREF and the digital output of the AD9243, see
Table IV.
Refer to Table I and Table II for a summary of the various
analog input and reference configurations.
ANALOG INPUT OPERATION
Figure 21 shows the equivalent analog input of the AD9243
which consists of a differential sample-and-hold amplifier (SHA).
The differential input structure of the SHA is highly flexible,
allowing the devices to be easily configured for either a differen-
tial or single-ended input. The dc offset, or common-mode
voltage, of the input(s) can be set to accommodate either single-
supply or dual supply systems. Also, note that the analog inputs,
VINA and VINB, are interchangeable with the exception that
reversing the inputs to the VINA and VINB pins results in a
polarity inversion.
CS
QS1
QH1
VINA
VINB
CS
QS1
CPIN
CPAR
CPIN+
CPAR
QS2
CH
QS2
CH
Figure 21. AD9243 Simplified Input Circuit
INTRODUCTION
The AD9243 utilizes a four-stage pipeline architecture with a
wideband input sample-and-hold amplifier (SHA) implemented
on a cost-effective CMOS process. Each stage of the pipeline,
excluding the last stage, consists of a low resolution flash A/D
connected to a switched capacitor DAC and interstage residue
amplifier (MDAC). The residue amplifier amplifies the differ-
ence between the reconstructed DAC output and the flash input
for the next stage in the pipeline. One bit of redundancy is used
in each of the stages to facilitate digital correction of flash er-
rors. The last stage simply consists of a flash A/D.
The pipeline architecture allows a greater throughput rate at the
expense of pipeline delay or latency. This means that while the
converter is capable of capturing a new input sample every clock
cycle, it actually takes three clock cycles for the conversion to be
fully processed and appear at the output. This latency is not a
concern in most applications. The digital output, together with
the out-of-range indicator (OTR), is latched into an output
buffer to drive the output pins. The output drivers can be con-
figured to interface with +5 V or +3.3 V logic families.
The AD9243 uses both edges of the clock in its internal timing
circuitry (see Figure 1 and specification page for exact timing
requirements). The A/D samples the analog input on the rising
edge of the clock input. During the clock low time (between the
falling edge and rising edge of the clock), the input SHA is in
the sample mode; during the clock high time it is in the hold
mode. System disturbances just prior to the rising edge of the
clock and/or excessive clock jitter may cause the input SHA to
acquire the wrong value, and should be minimized.
ANALOG INPUT AND REFERENCE OVERVIEW
Figure 20, a simplified model of the AD9243, highlights the rela-
tionship between the analog inputs, VINA, VINB, and the
reference voltage, VREF. Like the voltage applied to the top
of the resistor ladder in a flash A/D converter, the value VREF
defines the maximum input voltage to the A/D core. The minimum
input voltage to the A/D core is automatically defined to be –VREF.
VCORE
VINA
VINB
+VREF
–VREF
A/D
CORE
14
AD9243
Figure 20. AD9243 Equivalent Functional Input Circuit
The addition of a differential input structure gives the user an
additional level of flexibility that is not possible with traditional
flash converters. The input stage allows the user to easily config-
ure the inputs for either single-ended operation or differential
operation. The A/D’s input structure allows the dc offset of the
input signal to be varied independently of the input span of the
converter. Specifically, the input to the A/D core is the difference
of the voltages applied at the VINA and VINB input pins.


Ähnliche Teilenummer - AD9243EB

HerstellerTeilenummerDatenblattBauteilbeschribung
logo
Analog Devices
AD9243EB AD-AD9243EB Datasheet
545Kb / 24P
   Complete 14-Bit, 3.0 MSPS Monolithic A/D Converter
REV. A
AD9243EB AD-AD9243EB Datasheet
403Kb / 24P
   Complete 14-Bit, 3.0 MSPS Monolithic A/D Converter
REV. A
More results

Ähnliche Beschreibung - AD9243EB

HerstellerTeilenummerDatenblattBauteilbeschribung
logo
Analog Devices
AD9243ASZ AD-AD9243ASZ Datasheet
403Kb / 24P
   Complete 14-Bit, 3.0 MSPS Monolithic A/D Converter
REV. A
AD9243 AD-AD9243 Datasheet
545Kb / 24P
   Complete 14-Bit, 3.0 MSPS Monolithic A/D Converter
REV. A
AD9243ASRL AD-AD9243ASRL Datasheet
403Kb / 24P
   Complete 14-Bit, 3.0 MSPS Monolithic A/D Converter
REV. A
AD9243 AD-AD9243_15 Datasheet
403Kb / 24P
   Complete 14-Bit, 3.0 MSPS Monolithic A/D Converter
REV. A
AD9824 AD-AD9824_15 Datasheet
439Kb / 24P
   Complete 14-Bit 30 MSPS CCD Signal Processor
REV. 0
AD9824KCPZ AD-AD9824KCPZ Datasheet
387Kb / 24P
   Complete 14-Bit 30 MSPS CCD Signal Processor
REV. 0
AD9824 AD-AD9824 Datasheet
438Kb / 24P
   Complete 14-Bit 30 MSPS CCD Signal Processor
REV. 0
AD9241 AD-AD9241 Datasheet
495Kb / 24P
   Complete 14-Bit, 1.25 MSPS Monolithic A/D Converter
REV. 0
AD9241 AD-AD9241_17 Datasheet
530Kb / 25P
   Complete 14-Bit, 1.25 MSPS Monolithic A/D Converter
AD9240 AD-AD9240 Datasheet
328Kb / 24P
   Complete 14-Bit, 10 MSPS Monolithic A/D Converter
REV. A
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25


Datenblatt Download

Go To PDF Page


Link URL




Privatsphäre und Datenschutz
ALLDATASHEETDE.COM
War ALLDATASHEET hilfreich?  [ DONATE ] 

Über Alldatasheet   |   Werbung   |   Kontakt   |   Privatsphäre und Datenschutz   |   Linktausch   |   Hersteller
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com