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AD5337ARM-REEL7 Datenblatt(PDF) 1 Page - Analog Devices |
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AD5337ARM-REEL7 Datenblatt(HTML) 1 Page - Analog Devices |
1 / 24 page 2.5 V to 5.5 V, 250 µA, 2-Wire Interface Dual-Voltage Output, 8-/10-/12-Bit DACs AD5337/AD5338/AD5339 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. FEATURES AD5337 2 buffered 8-bit DACs in 8-lead MSOP AD5338, AD5338-1 2 buffered 10-bit DACs in 8-lead MSOP AD5339 2 buffered 12-bit DACs in 8-lead MSOP Low power operation: 250 mA @ 3 V, 300 mA @ 5 V 2-wire (I2C®compatible) serial interface 2.5 V to 5.5 V power supply Guaranteed monotonic by design over all codes Power-down to 80 nA @ 3 V, 200 nA @ 5 V 3 power-down modes Double-buffered input logic Output range: 0 V to VREF Power-on reset to 0 V Simultaneous update of outputs (LDAC function) Software clear facility Data readback facility On-chip rail-to-rail output buffer amplifiers Temperature range −40°C to +105°C APPLICATIONS Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators Industrial process control GENERAL DESCRIPTION AD5337/AD5338/AD5339 are dual 8-, 10-, and 12-bit buffered voltage output DACs in an 8-lead MSOP package, which operate from a single 2.5 V to 5.5 V supply, consuming 250 µA at 3 V. On-chip output amplifiers allow rail-to-rail output swing with a slew rate of 0.7 V/µs. A 2-wire serial interface operates at clock rates up to 400 kHz. This interface is SMBus-compatible at VDD < 3.6 V. Multiple devices can be placed on the same bus. The references for the two DACs are derived from one reference pin. The outputs of all DACs may be updated simultaneously using the software LDAC function. The parts incorporate a power-on reset circuit that ensures that the DAC outputs power up to 0 V and remain there until a valid write to the device takes place. A software clear function resets all input and DAC registers to 0 V. A power-down feature reduces the current consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V). The low power consumption of these parts in normal operation makes them ideally suited to portable battery-operated equipment. The power consumption is typically 1.5 mW at 5 V and 0.75 mW at 3 V, reducing to 1 µW in power-down mode. FUNCTIONAL BLOCK DIAGRAM SCL INTERFACE LOGIC INPUT REGISTER VOUTA BUFFER DAC REGISTER STRING DAC A VDD REFIN INPUT REGISTER VOUTB BUFFER DAC REGISTER POWER-ON RESET POWER-DOWN LOGIC LDAC STRING DAC B A0 SDA GND AD5337/AD5338/AD5339 Figure 1. |
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