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ADN2811ACP-CML Datenblatt(PDF) 11 Page - Analog Devices

Teilenummer ADN2811ACP-CML
Bauteilbeschribung  OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp
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ADN2811ACP-CML Datenblatt(HTML) 11 Page - Analog Devices

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REV. A
ADN2811
–11–
An on-chip oscillator to be used with an external crystal is also
provided as an alternative to using the REFCLKN/P inputs.
Details of the recommended crystal are given in Table III.
Table II. Reference Frequency Selection
Applied Reference
REFSEL
REFSEL[1..0]
Frequency (MHz)
100
19.44
101
38.88
110
77.76
111
155.52
0XX
REFCLKP/N Inactive. Use
19.44 MHz XTAL oscillator
on Pins XO1, XO2 (Pull
REFCLKP to VCC).
Table III. Required Crystal Specifications
Parameter
Value
Mode
Series Resonant
Frequency/Overall Stability
19.44 MHz
± 100 ppm
Frequency Accuracy
± 100 ppm
Temperature Stability
± 100 ppm
Aging
± 100 ppm
ESR
20
Ω max
Recommended Manufacturer:
Raltron (305) 593-6033
Part Number: H10S-19.440-S-EXT
REFSEL must be tied to VCC when the REFCLKN/P inputs
are active or tied to VEE when the oscillator is used. No
connection between the XO pin and REFCLK input is necessary
(see Figures 12–14). Note that the crystal should operate in series
resonant mode, which renders it insensitive to external parasitics.
No trimming capacitors are required.
Lock Detector Operation
The lock detector monitors the frequency difference between
the VCO and the reference clock and deasserts the loss of lock
signal when the VCO is within 500 ppm of center frequency
(see Figure 15). This enables the phase loop, which pulls the
VCO frequency in the remaining amount and also acquires
phase lock. Once locked, if the input frequency error exceeds
1000 ppm (0.1%), the loss of lock signal is reasserted and con-
trol returns to the frequency loop, which will reacquire and
maintain a stable clock signal at the output.
1000
500
0
500
1000
fVCO ERROR
(ppm)
LOL
1
Figure 15. Transfer Function of LOL
The frequency loop requires a single external capacitor between
CF1 and CF2. The capacitor specification is given in Table IV.
Table IV. Recommended CF Capacitor Specification
Parameter
Value
Temperature Range
–40 C to +85 C
Capacitance
>3.0
µF
Leakage
<80 nA
Rating
>6.3 V
Recommended Manufacturer:
Murata Electronics (770) 436-1300
Part Number: GRM32RR71C475LC01
Squelch Mode
When the squelch input is driven to a TTL high state, both the
clock and data outputs are set to the zero state to suppress
downstream processing. If desired, this pin can be directly
driven by the LOS detector output, SDOUT. If the squelch func-
tion is not required, the pin should be tied to VEE.
Test Modes: Bypass and Loopback
When the bypass input is driven to a TTL high state, the
quantizer output is connected directly to the buffers driving the data
out pins, thus bypassing the clock recovery circuit (see Figure 16).
This feature can help the system to deal with nonstandard bit rates.
The Loopback Mode can be invoked by driving the LOOPEN
Pin to a TTL high state, which facilitates system diagnostic test-
ing. This will connect the test inputs (TDINP/N) to the clock
and data recovery circuit (per Figure 16). The test inputs have
internal 50
Ω terminations and can be left floating when not in
use. TDINP/N are CML inputs and can only be dc-coupled
when being driven by CML outputs. The TDINP/N inputs must
be ac-coupled if being driven by anything other than CML out-
puts. Bypass and loopback modes are mutually exclusive. Only
one of these modes can be used at any given time. The
ADN2811 will be put into an indeterminate state if both
BYPASS and LOOPEN pins are set to Logic 1 at the same time.


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