AD8452

Data Sheet

Rev. 0 | Page 10 of 34

Pin No.

Mnemonic

Description

25

CLFLG

Output

Current-Limit Flag. CLFLG goes low and stays low when the AD8452 is in current limit mode.

Connect a 10 kΩ (minimum) resistor to the VREG pin.

26

SYNC

Input/

output

C lock Synchronization Pin. Synchronizes the clock (switching frequency) when multiple channels

are phase interleaved. Connect a 10 kΩ (minimum) resistor to the VREG pin.

27

SCFG

Input/

output

Synchronization Configuration Pin. See Table 10.

28

VREG

Output

Internal LDO 5 V Regulator Output and Internal Bias Supply. Connect a bypass capacitor of 1 µF or

greater from this pin to ground.

29

VIN

Input

Supply Voltage to the PWM Section. VIN is typically the same as the output switch supply voltage.

30

DL

Output

Logic Drive Output for the External Low-Side Metal-Oxide Semiconductor Field-Effect Transistor

(MOSFET) Driver.

31

DH

Output

Logic Drive Output for the External High-Side MOSFET Driver.

32

DGND

N/A

Digital and PWM Ground.

33

DT

Output

Dead Time Programming Pin. Connect an external resistor between this pin and ground to set the

dead time. Do not leave this pin floating.

34

SS

Output

Soft Start Control Pin. A capacitor connected from the SS pin to ground sets the soft start ramp

time. See the Selecting CSS section.

35

DMAX

Input

Maximum Duty Cycle Input. Connect an external resistor to ground to set the maximum duty

cycle. If the 97% internal maximum duty cycle is sufficient for the application, tie this pin to VREG.

If DMAX is left floating, this pin is internally pulled up to VREG.

36

FREQ

N/A

Frequency Set Pin. Connect an external resistor between this pin and ground to set the frequency

between 50 kHz and 300 kHz. When the AD8452 is synchronized to an external clock (slave mode), set

37

CLVT

Input

Current-Limit Voltage Threshold. With user selected resistor value, CLVT establishes a threshold

voltage for the current limit comparator. See the Select RCL and RCLVT for the Peak Current Limit

section.

38

CLP

Input

Current-Limit/Diode Emulation Amplifier Positive Sense Pin.

39

CLN

Input

Current-Limit/Diode Emulation Amplifier Negative Sense Pin.

40, 46

AVCC

N/A

Analog Positive Supply Pins.

42

IVE1

Input

Inverting Input of the CC Loop Filter Amplifier When in Charge Mode.

43

IVE0

Input

Inverting Input of the CC Loop Filter Amplifier When in Discharge Mode.

44

ISMEA

Output

Current Sense Instrumentation Amplifier Output.

45

ISET

Input

Scaled CC Voltage Loop Control Input for Battery Charge or Discharge Cycles. ISET is typically the

same for charge and discharge cycle.

47

AGND

N/A

Analog Ground.

48

VREF

Output

2.5 V Reference. Bypass this pin with a high quality 10 nF NP0 ceramic capacitor in series with a

10 Ω (maximum) resistor.

1

N/A means not applicable.