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AD9675 Datenblatt(PDF) 11 Page - Analog Devices |
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AD9675 Datenblatt(HTML) 11 Page - Analog Devices |
11 / 61 page AD9675 Data Sheet Rev. A | Page 10 of 60 Parameter1 Temperature Min Typ Max Unit LO GENERATION MLO± Frequency 4LO Mode Full 4 40 MHz 8LO Mode Full 8 80 MHz 16LO Mode Full 16 160 MHz RESET± to MLO± Setup Time (tSETUP) Full 1 tMLO/2 ns RESET± to MLO± Hold Time (tHOLD) Full 1 tMLO/2 ns 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 Can be adjusted via the SPI. 3 Mode III must have the RF decimator enabled. 4 Mode IV must have the RF decimator enabled. 5 PLL lock time from 0 Hz to 40 MHz frequency change. 6 Wake-up time is defined as the time required to return to normal operation from power-down mode. CLK±, TX_TRIG± Synchronization Timing Diagram Figure 2. TX_TRIG± to CLK± Input Timing CW Timing Diagram Figure 3. CW Doppler Mode Input MLO±, Continuous Synchronous RESET± Timing, Sampled on the Falling MLO± Edge, 4LO Mode Figure 4. CW Doppler Mode Input MLO±, Continuous Synchronous RESET± Timing, Sampled on the Falling MLO± Edge, 8LO Mode CLK– CLK+ TX_TRIG+ TX_TRIG– tEH tEL tSETUP tHOLD MLO– MLO+ RESET– RESET+ tMLO tSETUP tHOLD MLO– MLO+ RESET– RESET+ tMLO tHOLD tSETUP |
Ähnliche Teilenummer - AD9675 |
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Ähnliche Beschreibung - AD9675 |
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