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SDA 9388X Block Diagram

The SDA 9388X integrates different functional blocks on a single chip

Availability

Samples of the SDA 9388X are available with complete documentation

for evaluation. SIEMENS’ highly experienced engineering support team

can assist you with your design in work. Please contact your local

Siemens office for further details.

SDA 9388X Application Example

AD Converter

decoder

peaking

and memory control logic

REFL

V

REFH

V

CVBS2

CVBS1

CVBS3

Source

Select

Clamp

7-Bit ADC

Gain

Control

NTSC/PAL

Chroma

Decoder

DDA 1

V

SSA 1

V

Y

UY

Low-

pass

Filter

M

U

X

DD

V

SS

V

PIP Field

Memory

Line Memory

Output Signal

Processing

RGB Matrix

Framing

Triple

DAC

6-Bit

D

E

M

U

X

v/r

y/g

u/b

6

6

6

V

REF

V

R/V

G/Y

(OUT)

B/U

BLK

R

G

(IN)

B

SEL

Closed

Caption

Data Slicer

*

Parent

Clock

Gen

Clock Generation

(Quarz Oszillator)

Controller

SCP

VP/SCP

SCL

SDA

XIN

XQ

XFREQ

Analog

Functions

Patent Sync Signal Processing

Parent

Clock

Generation

Picture

Position

Control

RGB

Switch

3

Inset

Synchronization

Read/Write

Controller

Tuner 1

Tuner 2

CVBS 1

CVBS 2

CVBS 3

(e.g. VCR)

(e.g. SAT)

PIP III

SDA 9388X

Select

G/Y

B/U

R/V

Teletext or

OSD processor

(optional)

RG B

BLK

Sync

RGB-

Processor

R

G

B

R/V

G/Y

B/U

Color Decoder

for Main Channel

CVBS

Ordering No. B110-H7264-X-X-7600

Printed in Germany

PS 08983.

“With our on-chip system solutions

we are providing innovative, in every

respect optimized key products for

the multimedia age. In so doing

Siemens Semiconductors is going

to get one of the major players

in the market of logic ICs.”

Dr. S. Mehrgardt,

President,

Siemens Semiconductors

Signal Processing Division