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SLG46533 Datenblatt(PDF) 99 Page - Dialog Semiconductor |
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SLG46533 Datenblatt(HTML) 99 Page - Dialog Semiconductor |
99 / 185 page SLG46533_DS_114 Page 98 of 184 SLG46533 9.9.1 WS Register Settings Table 91. WS Register Settings Signal Function Register Bit Address Register Definition Counter/delay0 Clock Source Select reg<1316:1314> 000: Internal OSC clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: 25MHz OSC clock 110: External Clock 111: Counter6 Overflow WS time selection reg<1489> 0: Short Wake Time 1: Normal Wake Time ACMP0 Wake & Sleep function Enable reg<1490> 0: Disable 1: Enable ACMP1 Wake & Sleep function Enable reg<1491> 0: Disable 1: Enable ACMP2 Wake & Sleep function Enable reg<1492> 0: Disable 1: Enable ACMP3 Wake & Sleep function Enable reg<1493> 0: Disable 1: Enable Wake Sleep Output State When WS Oscillator is Power Down if DLY/CNT0 Mode Selection is "11" reg<1494> 0: Low 1: High Wake Sleep Ratio Control Mode Selection if DLY/CNT0 Mode Selection is "11" reg<1495> 0: Default Mode 1: Wake Sleep Ratio Control Mode DLY/CNT0 (16bits, <15:0> = <1591:1576>) Control Data reg<1591:1576> 1 - 65535 |
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