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SDA9290-5 Datenblatt(PDF) 4 Page - Siemens Semiconductor Group |
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SDA9290-5 Datenblatt(HTML) 4 Page - Siemens Semiconductor Group |
4 / 22 page SDA 9290-5 Semiconductor Group 262 I2C Bus Interface An I2C Bus interface configured as a “slave receiver” is used for programming the different functions and modes of the picture processor. Via this interface up to four registers can be written according to the following transfer protocol for controlling the operation mode: S: Start condition A: Acknowledge P: Stop condition Slave address: 0 0 1 0 1 0 1 (Note: There is a general description of the I2C Bus in the Siemens publication “I2C Bus Technical Description”.) After every data byte that is transmitted the internal register address (subaddress) is automatically incremented to the next register so that, if necessary, several registers can be loaded with one I2C Bus telegram. In the multi-picture mode the operating mode transmitted on the I2C Bus is switched within the vertical blanking interval, i.e. during the high phase of signal VS1, if the Memory Sync Controller (MSC) activates the DREQ line during this period. It should be noted that the new operating mode has always to be transmitted to the picture processor first and immediately afterwards to the MSC on the I2C Bus at an interval not longer than 30 ms. This is the only way to ensure interference-free synchronization of the picture processor and the MSC. The four I2C Bus registers are described below in more detail. The values marked “*D” in the right-hand margin are set by an internally generated reset signal (default values) when the operating voltage is applied. Register Sub- address1) Data Byte D7 D6 D5 D4 D3 D2 D1 D0 R0 00 B1 B0 FR 0 SS VCR NR SUV8 R1 01 YF5 YF4 YF3 SL4 SL3 SL2 SL1 SL0 R2 02 0 0 0 SU4 SU3 SU2 SU1 SU0 R3 03 SNTEN SNT1 SNT0 KTEN KT3 KT2 KT1 KT0 S 0 AAA A P Slave Address Sub Address Data Byte |
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