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SN74AUP1T97 Datenblatt(PDF) 3 Page - Texas Instruments |
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SN74AUP1T97 Datenblatt(HTML) 3 Page - Texas Instruments |
3 / 15 page SN74AUP1T97 SINGLESUPPLY VOLTAGE LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS SCES613A – OCTOBER 2004 − REVISED DECEMBER 2004 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Figure 1. AUP - The Lowest-Power Family AUP LVC AUP AUP LVC Static-Power Consumption ( µA) Dynamic-Power Consumption (pF) † Single, dual, and triple gates 3.3-V Logic† 3.3-V Logic† 0% 20% 40% 60% 80% 100% 0% 20% 40% 60% 80% 100% −0.5 0 0.5 1 1.5 2 2.5 3 3.5 05 10 15 20 25 30 35 40 45 Figure 2. Excellent Signal Integrity Time − ns † AUP1G08 data at C L = 15 pF Switching Characteristics at 25 MHz† Output Input 1.8-V System 3.3-V System VIH = 1.19 V VIL = 0.5 V 3.3 V 2.5-V System 3.3-V System VIH = 1.19 V VIL = 0.5 V 3.3 V 1.8-V System 2.5-V System VIH = 1.10 V VIL = 0.35 V 2.5 V 3.3-V System 2.5-V System VIH = 1.10 V VIL = 0.35 V 2.5 V AUP1T97 AUP1T97 AUP1T97 AUP1T97 Figure 3. Possible Voltage Translation Combinations 1.8-V System 3.3-V System 3.3 V AUP1T97 VT+(max) = VIH(min) = 1.19 V VT−(min) = VIL(max) = 0.5 V VOH min VOL max Input Switching Waveform Output Switching Waveform Figure 4. Switching Thresholds for 1.8-V to 3.3-V Translation |
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