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CY7C1618KV18 Datenblatt(PDF) 6 Page - Cypress Semiconductor |
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CY7C1618KV18 Datenblatt(HTML) 6 Page - Cypress Semiconductor |
6 / 32 page Document Number: 001-44274 Rev. *N Page 6 of 32 CY7C1618KV18/CY7C1620KV18 Functional Overview The CY7C1618KV18, and CY7C1620KV18 are synchronous pipelined burst SRAMs equipped with a DDR interface, which operates with a read latency of one and a half cycles when DOFF pin is tied high. When DOFF pin is set low or connected to VSS, the device behaves in DDR I mode with a read latency of one clock cycle. Accesses are initiated on the rising edge of the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the rising edge of the output clocks (C/C, or K/K when in single clock mode). All synchronous data inputs (D[x:0]) pass through input registers controlled by the rising edge of the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the output clocks (C/C, or K/K when in single clock mode). All synchronous control (R/W, LD, BWS[0:X]) inputs pass through input registers controlled by the rising edge of the input clock (K). CY7C1618KV18 is described in the following sections. The same basic descriptions apply to CY7C1620KV18. Read Operations The CY7C1618KV18 is organized internally as two arrays of 2M × 18. Accesses are completed in a burst of 2 sequential 18-bit data words. Read operations are initiated by asserting R/W high and LD low at the rising edge of the positive input clock (K). The address presented to address inputs is stored in the read address register and the least significant bit of the address is presented to the burst counter. The burst counter increments the address in a linear fashion. Following the next K clock rise, the corresponding 18-bit word of data from this address location is driven onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C, the next 18-bit data word from the address location generated by the burst counter is driven onto the Q[17:0]. The requested data is valid 0.45 ns from the rising edge of the output clock (C or C, or K and K when in single clock mode). To maintain the internal logic, each read access must be enabled to complete. Read accesses can be initiated on every rising edge of the positive input clock (K). When read access is deselected, the CY7C1618KV18 first completes the pending read transactions. Synchronous internal circuitry automatically tristates the output, following the next rising edge of the positive output clock (C). This enables a transition between devices without the insertion of wait states in a depth expanded memory. Write Operations Write operations are initiated by asserting R/W low and LD low at the rising edge of the positive input clock (K). The address presented to address inputs is stored in the write address register and the least significant bit of the address is presented to the burst counter. The burst counter increments the address in a linear fashion. On the following K clock rise, the data presented to D[17:0] is latched and stored into the 18-bit write data register, provided BWS[1:0] are both asserted active. On the subsequent rising edge of the Negative Input Clock (K) the information presented to D[17:0] is also stored into the write data register, provided BWS[1:0] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. Write accesses can be initiated on every rising edge of the positive input clock (K). This pipelines the data flow so that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K). When the write access is deselected, the device ignores all inputs after the pending write operations have been completed. Byte Write Operations Byte write operations are supported by the CY7C1618KV18. A write operation is initiated as described in Write Operations on DOFF Input PLL turn Off Active low. Connecting this pin to ground turns off the PLL inside the device. The timing in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin can be connected to a pull-up through a 10 k or less pull-up resistor. The device behaves in DDR I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with DDR I timing. TDO Output Test data-out (TDO) pin for JTAG. TCK Input Test clock (TCK) pin for JTAG. TDI Input Test data-in (TDI) pin for JTAG. TMS Input Test mode select (TMS) pin for JTAG. NC N/A Not connected to the die: Can be tied to any voltage level. NC/288M Input Not connected to the die: Can be tied to any voltage level. VREF Input- Reference Reference voltage input: Static input used to set the reference level for HSTL inputs, outputs, and AC measurement points. VDD Power Supply Power supply inputs to the core of the device. VSS Ground Ground for the device. VDDQ Power Supply Power supply inputs for the outputs of the device. Pin Definitions (continued) Pin Name I/O Pin Description |
Ähnliche Teilenummer - CY7C1618KV18 |
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Ähnliche Beschreibung - CY7C1618KV18 |
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