Datenblatt-Suchmaschine für elektronische Bauteile
  German  ▼
ALLDATASHEETDE.COM

X  

CY7C1618KV18 Datenblatt(PDF) 12 Page - Cypress Semiconductor

Teilenummer CY7C1618KV18
Bauteilbeschribung  144-Mbit DDR II SRAM Two-Word Burst Architecture
Download  32 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Hersteller  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1618KV18 Datenblatt(HTML) 12 Page - Cypress Semiconductor

Back Button CY7C1618KV18 Datasheet HTML 8Page - Cypress Semiconductor CY7C1618KV18 Datasheet HTML 9Page - Cypress Semiconductor CY7C1618KV18 Datasheet HTML 10Page - Cypress Semiconductor CY7C1618KV18 Datasheet HTML 11Page - Cypress Semiconductor CY7C1618KV18 Datasheet HTML 12Page - Cypress Semiconductor CY7C1618KV18 Datasheet HTML 13Page - Cypress Semiconductor CY7C1618KV18 Datasheet HTML 14Page - Cypress Semiconductor CY7C1618KV18 Datasheet HTML 15Page - Cypress Semiconductor CY7C1618KV18 Datasheet HTML 16Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 12 / 32 page
background image
Document Number: 001-44274 Rev. *N
Page 12 of 32
CY7C1618KV18/CY7C1620KV18
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard 1149.1-2001. The TAP operates using JEDEC
standard 1.8 V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied low
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternatively be connected to VDD through a pull-up resistor. TDO
must be left unconnected. Upon power up, the device comes up
in a reset state, which does not interfere with the operation of the
device.
Test Access Port
Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a Logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
instruction loaded into the TAP instruction register, chooses the
register between TDI and TDO. For information about loading
the instruction register, see the TAP Controller State Diagram on
page 14. TDI is internally pulled up and can be unconnected if
the TAP is unused in an application. TDI is connected to the most
significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 18).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS high (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and can be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a High Z state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 15. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to enable fault
isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, you
can skip certain chips. The bypass register is a single-bit register
that is placed between TDI and TDO pins. This enables shifting
of data through the SRAM with minimal delay. The bypass
register is set low (VSS) when the BYPASS instruction is
executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
The Boundary Scan Order on page 19 shows the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 18.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 18. Three of these instructions are listed as
RESERVED and cannot be used. The other five instructions are
described in this section in detail.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller is moved
into the Update-IR state.


Ähnliche Teilenummer - CY7C1618KV18

HerstellerTeilenummerDatenblattBauteilbeschribung
logo
Cypress Semiconductor
CY7C1618KV18-300BZXC CYPRESS-CY7C1618KV18-300BZXC Datasheet
1Mb / 32P
   144-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1618KV18-333BZXC CYPRESS-CY7C1618KV18-333BZXC Datasheet
1Mb / 32P
   144-Mbit DDR II SRAM Two-Word Burst Architecture
More results

Ähnliche Beschreibung - CY7C1618KV18

HerstellerTeilenummerDatenblattBauteilbeschribung
logo
Cypress Semiconductor
CY7C161KV18 CYPRESS-CY7C161KV18 Datasheet
1Mb / 32P
   144-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1623KV18 CYPRESS-CY7C1623KV18 Datasheet
773Kb / 28P
   144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture
CY7C1625KV18 CYPRESS-CY7C1625KV18 Datasheet
894Kb / 33P
   144-Mbit QDR짰 II SRAM Two-Word Burst Architecture
CY7C1518AV18 CYPRESS-CY7C1518AV18_11 Datasheet
1Mb / 29P
   72-Mbit DDR-II SRAM Two-Word Burst Architecture
CY7C1418KV18 CYPRESS-CY7C1418KV18_12 Datasheet
1Mb / 31P
   36-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1316KV18 CYPRESS-CY7C1316KV18 Datasheet
1,019Kb / 32P
   18-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1648KV18 CYPRESS-CY7C1648KV18_12 Datasheet
857Kb / 30P
   144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1668KV18 CYPRESS-CY7C1668KV18 Datasheet
771Kb / 30P
   144-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1648KV18 CYPRESS-CY7C1648KV18 Datasheet
783Kb / 29P
   144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1523KV18 CYPRESS-CY7C1523KV18_13 Datasheet
792Kb / 28P
   72-Mbit DDR II SIO SRAM Two-Word Burst Architecture
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32


Datenblatt Download

Go To PDF Page


Link URL




Privatsphäre und Datenschutz
ALLDATASHEETDE.COM
War ALLDATASHEET hilfreich?  [ DONATE ] 

Über Alldatasheet   |   Werbung   |   Kontakt   |   Privatsphäre und Datenschutz   |   Linktausch   |   Hersteller
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com