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CY7C1618KV18 Datenblatt(PDF) 21 Page - Cypress Semiconductor

Teilenummer CY7C1618KV18
Bauteilbeschribung  144-Mbit DDR II SRAM Two-Word Burst Architecture
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Hersteller  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1618KV18 Datenblatt(HTML) 21 Page - Cypress Semiconductor

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Document Number: 001-44274 Rev. *N
Page 21 of 32
CY7C1618KV18/CY7C1620KV18
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to GND .......–0.5 V to +2.9 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
DC applied to outputs in High Z ........ –0.5 V to VDDQ + 0.3 V
DC input voltage [19] ........................... –0.5 V to VDD + 0.3 V
Current into outputs (Low) .......................................... 20 mA
Static discharge voltage
(MIL-STD-883, M. 3015) ......................................... > 2001 V
Latch up current ..................................................... > 200 mA
Operating Range
Range
Ambient
Temperature (TA)
VDD [20]
VDDQ [20]
Commercial
0 °C to +70 °C
1.8 ± 0.1 V
1.4 V to
VDD
Industrial
–40 °C to +85 °C
Neutron Soft Error Immunity
Parameter
Description
Test
Conditions Typ Max* Unit
LSBU
Logical
single-bit
upsets
25 °C
197
216
FIT/
Mb
LMBU
Logical
multi-bit
upsets
25 °C
0
0.01
FIT/
Mb
SEL
Single event
latch up
85 °C
0
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
statistical
2, 95% confidence limit calculation. For more details refer to Application
Note Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates
– AN54908.
Electrical Characteristics
Over the Operating Range
DC Electrical Characteristics
Over the Operating Range
Parameter [21]
Description
Test Conditions
Min
Typ
Max
Unit
VDD
Power supply voltage
1.7
1.8
1.9
V
VDDQ
I/O supply voltage
1.4
1.5
VDD
V
VOH
Output high voltage
Note 22
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOL
Output low voltage
Note 23
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOH(LOW)
Output high voltage
IOH =0.1 mA, Nominal impedance
VDDQ – 0.2
VDDQ
V
VOL(LOW)
Output low voltage
IOL = 0.1 mA, Nominal impedance
VSS
–0.2
V
VIH
Input high voltage
VREF + 0.1
VDDQ + 0.3
V
VIL
Input low voltage
–0.3
VREF – 0.1
V
IX
Input leakage current
GND
 VI  VDDQ
5–
5
A
IOZ
Output leakage current
GND
 VI  VDDQ, Output disabled
5–
5
A
VREF
Input reference voltage [24] Typical Value = 0.75 V
0.68
0.75
0.95
V
Notes
19. Overshoot: VIH(AC) < VDDQ + 0.85 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 1.5 V (Pulse width less than tCYC/2).
20. Power up: assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
21. All voltage referenced to ground.
22. Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175 < RQ < 350 .
23. Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 < RQ < 350 .
24. VREF(min) = 0.68 V or 0.45 VDDQ, whichever is larger, VREF(max) = 0.95 V or 0.54 VDDQ, whichever is smaller.


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