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CY7C1618KV18 Datenblatt(PDF) 25 Page - Cypress Semiconductor

Teilenummer CY7C1618KV18
Bauteilbeschribung  144-Mbit DDR II SRAM Two-Word Burst Architecture
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Hersteller  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1618KV18 Datenblatt(HTML) 25 Page - Cypress Semiconductor

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Document Number: 001-44274 Rev. *N
Page 25 of 32
CY7C1618KV18/CY7C1620KV18
Output Times
tCO
tCHQV
C/C clock rise (or K/K in single
clock mode) to data valid
0.45
0.45
0.45
ns
tDOH
tCHQX
Data output hold after output C/C
clock rise (active to active)
–0.45
–0.45
–0.45
ns
tCCQO
tCHCQV
C/C clock rise to echo clock valid
0.45
0.45
0.45
ns
tCQOH
tCHCQX
Echo clock hold after C/C clock
rise
–0.45
–0.45
–0.45
ns
tCQD
tCQHQV
Echo clock high to data valid
0.25
0.27
0.30
ns
tCQDOH
tCQHQX
Echo clock high to data invalid
–0.25
–0.27
–0.30
ns
tCQH
tCQHCQL
Output clock (CQ/CQ) high [32]
1.25
1.40
1.75
ns
tCQHCQH
tCQHCQH
CQ clock rise to CQ clock rise
(rising edge to rising edge) [32]
1.25
1.40
1.75
ns
tCHZ
tCHQZ
Clock (C/C) rise to High Z (Active
to High Z) [33, 34]
0.45
0.45
0.45
ns
tCLZ
tCHQX1
Clock (C/C) rise to Low Z [33, 34]
–0.45
–0.45
–0.45
ns
PLL Timing
tKC Var
tKC Var
Clock phase jitter
0.20
0.20
0.20
ns
tKC lock
tKC lock
PLL lock time (K, C)
20
20
20
s
tKC Reset
tKC Reset
K static to PLL reset
30
30
30
ns
Switching Characteristics (continued)
Over the Operating Range
Parameters [29, 30]
Description
333 MHz
300 MHz
250 MHz
Unit
Cypress
Parameter
Consortium
Parameter
Min
Max
Min
Max
Min
Max
Notes
32. These parameters are extrapolated from the input timing parameters (tCYC/2 – 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
design and are not tested in production.
33. tCHZ, tCLZ are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 23. Transition is measured 100 mV from steady-state voltage.
34. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.


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