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CY7C1663KV18 Datenblatt(PDF) 20 Page - Cypress Semiconductor

Teilenummer CY7C1663KV18
Bauteilbeschribung  144-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
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Hersteller  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1663KV18 Datenblatt(HTML) 20 Page - Cypress Semiconductor

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Document Number: 001-44060 Rev. *O
Page 20 of 31
CY7C1663KV18/CY7C1665KV18
Power Up Sequence in QDR II+ SRAM
QDR II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power Up Sequence
Apply power and drive DOFF either high or low (all other inputs
can be high or low).
Apply VDD before VDDQ.
Apply VDDQ before VREF or at the same time as VREF.
Drive DOFF high.
Provide stable DOFF (high), power and clock (K, K) for 20 s
to lock the PLL
PLL Constraints
PLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var.
The PLL functions at frequencies down to 120 MHz.
If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 20
s of stable clock to
relock to the desired clock frequency.
Figure 4. Power Up Waveforms
> 20μs Stable clock
Start Normal
Operation
DOFF
Stable (< +/- 0.1V DC per 50ns )
Fix HIGH (or tie to VDDQ)
K
K
DDQ
DD
V
V
/
DDQ
DD
V
V
/
Clock Start (Clock Starts after
Stable)
DDQ
DD
V
V
/
Unstable Clock


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