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MP2141N Datenblatt(PDF) 13 Page - Monolithic Power Systems |
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MP2141N Datenblatt(HTML) 13 Page - Monolithic Power Systems |
13 / 19 page MP2141N – 1A, SYNCHRONOUS, STEP-DOWN CONVERTER WITH 11µA I Q MP2141N Rev. 1.12 www.MonolithicPower.com 13 7/28/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. OPERATION The MP2141N uses constant-on-time control with an input voltage feed-forward to stabilize the switching frequency over the full input range. It achieves 1A of continuous output current from a 2.3V-to-5.5V input voltage range with excellent load and line regulation. The output voltage can be regulated as low as 0.6V. Constant-on-Time Control Compared to fixed-frequency PWM control, constant-on-time control offers a simpler control loop and a faster transient response. By using an input voltage feed-forward, the MP2141N maintains a nearly constant switching frequency across the input and output voltage ranges. The switching pulse on time can be estimated with Equation (1): OUT ON IN V T 0.454 s V (1) To prevent inductor current runaway during the load transient, the MP2141N uses a fixed minimum off time of 60ns. Sleep Mode Operation The MP2141N features sleep mode to achieve high efficiency at extremely light loads. In sleep mode, most of the circuit blocks are turned off except the error amplifier and the PWM comparator. Therefore, the operation current is reduced to a minimal value (see Figure 2). Bias & Voltage Reference 0.6V FB + + - FBCOMP Soft start E.A. + - + Ramp generator SW Lo-Iq Lo-Iq Figure 2: Operation Blocks at Sleep Mode When the load becomes lighter, the output voltage ripple is bigger and drives the error amplifier output (EAO) lower. When the EAO hits an internal low threshold, it clamps at that level, and the MP2141N enters sleep mode. During sleep mode, the valley of the FB voltage is regulated to the internal reference voltage, making the average output voltage slightly higher than the output voltage at DCM or CCM. The on-time pulse at sleep mode is around 40% larger than that in DCM or CCM. Figure 3 shows the average FB voltage relationship with the internal reference at sleep mode. FB Vref Average FB Figure 3: FB Average Voltage at Sleep Mode When the MP2141N is in sleep mode, the average output voltage is higher than the internal reference voltage. The EAO is kept low and clamped in sleep mode. When the load increases, the PWM switching period decreases to keep the output voltage regulated, and the output voltage ripple decreases as well. Once the EAO is higher than the internal low threshold, the MP2141N exits sleep mode and enters DCM or CCM depending on the load. In DCM or CCM, the EAO regulates the average output voltage to the internal reference (see Figure 4). FB+ Ramp EA out Average FB= REF Figure 4: DCM Control There is always a loading hysteresis when entering sleep mode and exiting sleep mode due to the error amplifier clamping response time. AAM Operation at Light-Load Operation The MP2141N uses an advanced asynchronous modulation (AAM) power-save mode with a zero-current cross detection (ZCD) circuit for light loads. The MP2141N uses AAM power-save mode in light loads (see Figure 5). The AAM current (IAAM) is set internally. The SW on pulse time is decided by an on-time generator and AAM comparator. At light-load condition, SW on pulse time is stretched. The AAM comparator pulse is longer than the on-time generator. The mode of operation is shown below in Figure 6. |
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Ähnliche Beschreibung - MP2141N |
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