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S29GL01GP Datenblatt(PDF) 59 Page - Cypress Semiconductor |
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S29GL01GP Datenblatt(HTML) 59 Page - Cypress Semiconductor |
59 / 82 page Document Number: 002-00886 Rev. *B Page 59 of 83 S29GL01GP S29GL512P S29GL256P S29GL128P Notes 1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. 2. tOE for data polling is 45 ns when VIO = 1.65 to 2.7 V and is 35 ns when VIO = 2.7 to 3.6 V 3. CE# does not need to go high between status bit reads Figure 11.13 Toggle Bit Timings (During Embedded Algorithms) Note A = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle CE# does not need to go high between status bit reads Figure 11.14 DQ2 vs. DQ6 Note DQ2 toggles only when read at an address within an erase-suspended sector. The system can use OE# or CE# to toggle DQ2 and DQ6. OE# CE# WE# Addresses tOEH tDH tAHT tASO tOEPH tOE Valid Data (first read) (second read) (stops toggling) tCEPH tAHT tAS DQ2 and DQ6 Valid Data Valid Status Valid Status Valid Status RY/BY# Enter Erase Erase Erase Enter Erase Suspend Program Erase Suspend Read Erase Suspend Read Erase WE# DQ6 DQ2 Erase Complete Erase Suspend Suspend Program Resume Embedded Erasing |
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