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ADN2870ACPZ Datenblatt(PDF) 5 Page - Analog Devices |
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ADN2870ACPZ Datenblatt(HTML) 5 Page - Analog Devices |
5 / 20 page ADN2870 Rev. 0 | Page 5 of 20 SFP TIMING SPECIFICATIONS Table 2. Parameter Symbol Min Typ Max Unit Conditions/Comments ALS Assert Time t_off 1 5 µs Time for the rising edge of ALS (TX_DISABLE) to when the bias current falls below 10% of nominal. ALS Negate Time1 t_on 0.83 0.95 ms Time for the falling edge of ALS to when the modulation current rises above 90% of nominal. Time to Initialize, Including Reset of FAIL1 t_init 25 275 ms From power-on or negation of FAIL using ALS. FAIL Assert Time t_fault 100 µs Time to fault to FAIL on. ALS to Reset time t_reset 5 µs Time TX_DISABLE must be held high to reset TX_FAULT. 1 Guaranteed by design and characterization. Not production tested. DATAP DATAN DATAP–DATAN V p-p DIFF = 2 × VSE VSE 0V Figure 3. Signal Level Definition 0.1 µF 0.1 µF 10 µF 1 µH 3.3V SFP HOST BOARD SFP MODULE VCC_Tx Figure 4. Recommended SFP Supply |
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Ähnliche Beschreibung - ADN2870ACPZ |
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