3

HHH

↑

LL

H

D7

D7

H

H

H

H or L

L

L

H

H = High Voltage Level (Steady State); L = Low Voltage Level (Steady State);

↑ = Transition from Low to High Level;

before the most recent low-to-high transition of data control.

NOTE:

1. This column shows the input address setup with LE low.

TRUTH TABLE (Continued)

INPUTS

OUTPUTS

SELECT (NOTE 1)

CLOCK

OUTPUT ENABLES

S2

S1

S0

CP

OE1

OE2

OE3

YY

Block Diagram

15

D

A

T

A

R

E

G

I

S

T

E

R

S

1

8

O

F

S

E

L

E

C

T

O

R

ADDRESS

DECODE

AR

D

D

R

E

S

S

E

G

I

S

T

E

R

16

17

9

8

7

6

5

4

3

2

1

11

14

13

12

OE1

OE2

OE3

CP

D0

D1

D2

D3

D4

D5

D6

D7

LE

S0

S1

S2

19

18

Y

Y

BUFFERS

ENABLE LOGIC

CD74HCT356