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SN74AUP1G08DBVR Datenblatt(PDF) 2 Page - Texas Instruments |
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SN74AUP1G08DBVR Datenblatt(HTML) 2 Page - Texas Instruments |
2 / 13 page SN74AUP1G08 LOW POWER SINGLE 2INPUT POSITIVEAND GATE SCES502B − NOVEMBER 2003 − REVISED AUGUST 2004 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING‡ NanoStar − WCSP (DSBGA) 0.23-mm Large Bump − YEP Tape and reel SN74AUP1G08YEPR _ _ _HE_ −40 °C to 85°C NanoFree − WCSP (DSBGA) 0.23-mm Large Bump − YZP (Pb-free) Tape and reel SN74AUP1G08YZPR _ _ _HE_ SOT (SOT-23) − DBV Tape and reel SN74AUP1G08DBVR H08_ SOT (SC-70) − DCK Tape and reel SN74AUP1G08DCKR HE_ † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE INPUTS OUTPUT A B OUTPUT Y L L L L HL H LL H H H logic diagram (positive logic) 1 2 4 A B Y |
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