CYRUSTEK CO.

hold and low battery indication

The differential reference should be used during the measurement of resistor by the ratio-metric method and when a

digital reading of zero is desired for Vin 0, a compensating offset voltage can be applied between COMMON and INLO,

and the voltage of being measured is connected between COMMON and INHI.

3

System Timing

The oscillator frequency is divided by four prior to clocking the internal decade counters. The signal integration takes a

fixed 1000 counts time period which is equal to 4000 clock pulses. The back plane drive signal is derived by dividing

oscillator frequency by 800. To make a maximum noise rejection of line frequency(60Hz or 50Hz,) the signal integration

period should be a multiple of the line frequency period. For 60Hz-noise rejection, oscillator frequencies of 120KHz,

80KHz, 60KHz, 48KHz, 40KHz, etc. should be selected. For 50Hz rejection, oscillator frequencies of 100KHz, 50KHz,

40KHz, etc. would be suitable.

For all ranges of frequency Rosc should be 100K

, Cosc is selected from the approximate equation f 0.45/RC. For

48KHz clock (3reading/second), Cosc=100pF.

4

Integrating Resistor

The input buffer amplifier and integrator are designed with class A output stages.The output stage idling current is 100

uA. Both of them can supply 20uA drive currents with negligible linearity errors. The integrating resistor is chosen to

remain linear drive region in the output stage. It should not be so large that the leakage current of printed circuit board

will induce errors. The recommended integrating resistor value for the 200 mV and 2 V full-scale are 47K

and 470 K

respectively.

5

Integrating Capacitor

The integrating capacitor should be selected to maximize integrator output voltage swing without causing output satura-

tion. For 3 readings/second (48KHz clock,) a 0.22uF value of

is suggested. If a different oscillator frequency is

used,

must be changed in inverse proportion to maintain the nominal

2V integrator swing.

The integrating capacitor must have low dielectric absorption to minimize roll-over error. An inexpensive polypropy-

lene capacitor is re commented.

6

Auto-Zero Capacitor

The auto-zero capacitor size has some influence on system noise. A 0.47uF capacitor is recommended for 200mV full

scale. A 0.047uF capacitor is adequate for 2V full scale applications. A mylar type dielectric capacitor is adequate.

7

Reference Voltage Capacitor

The reference voltage used to ramp the integrator output voltage back to zero during the reference integrate cycle is stored

on

. A 0.1uF value capacitor is acceptable when INLO is connected with COMMON. A mylar type dielectric

capacitor is adequate.

8

TEST

The TEST pin is tied to the internally generated digital ground through a 500

resistor. Its potential is 5V less than V+.

The TEST pin load should be no more than 1 mA.

If TEST is pulled high to V+, all segments plus the minus sign will be actived. It may destroy the LCD display as

keeping in this mode for several minutes .

9

Segment Drivers

For 3 readings/second (48KHz clock) the BP frequency is a 60Hz square wave with a nominal amplitude of 5V. The

segments are driven in the same frequency/amplitude. They are in phase with BP when the segment should be OFF, but

out of phase when ON. The polarity indication is "ON" for negative voltage inputs.

7

July 21, 2003