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TL16C550DPFBR Datenblatt(PDF) 8 Page - Texas Instruments

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Teilenummer TL16C550DPFBR
Bauteilbeschribung  ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL
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Hersteller  TI [Texas Instruments]
Direct Link  http://www.ti.com
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TL16C550D, TL16C550DI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTOFLOW CONTROL
SLLS597C − APRIL 2004 − REVISED JUNE 2005
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (for PT and PFB packages)
TERMINAL
NAME
NUMBER
I/O
DESCRIPTION
A0
A1
A2
28
27
26
I
Register select. A0 − A2 are used during read and write operations to select the ACE register to read from or
write to. See Table 1 for register addresses, and see the ADS description.
ADS
24
I
Address strobe. When ADS is active (low), A0, A1, and A2 and CS0, CS1, and CS2 drive the internal select
logic directly; when ADS is high, the register select and chip select signals are held at the logic levels they were
in when the low-to-high transition of ADS occurred.
BAUDOUT
12
O
Baud out. BAUDOUT is a 16
× clock signal for the transmitter section of the ACE. The clock rate is established
by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches.
BAUDOUT may also be used for the receiver section by tying this output to RCLK.
CS0
CS1
CS2
9
10
11
I
Chip select. When CS0 and CS1 are high and CS2 is low, these three inputs select the ACE. When any of these
inputs are inactive, the ACE remains inactive (see the ADS description).
CTS
38
I
Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem
status register. Bit 0 (
∆CTS) of the modem status register indicates that CTS has changed states since the
last read from the modem status register. If the modem status interrupt is enabled when CTS changes levels
and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used in the auto-CTS mode to
control the transmitter.
D0
D1
D2
D3
D4
D5
D6
D7
43
44
45
46
47
2
3
4
I/O
Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
information between the ACE and the CPU.
DCD
40
I
Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the
modem status register. Bit 3 (
∆DCD) of the modem status register indicates that DCD has changed states
since the last read from the modem status register. If the modem status interrupt is enabled when DCD
changes levels, an interrupt is generated.
DDIS
22
O
Driver disable. DDIS is active (high) when the CPU is not reading data. When active, DDIS can disable an
external transceiver.
DSR
39
I
Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the
modem status register. Bit 1 (
∆DSR) of the modem status register indicates DSR has changed levels since
the last read from the modem status register. If the modem status interrupt is enabled when DSR changes
levels, an interrupt is generated.
DTR
33
O
Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish
communication. DTR is placed in the active level by setting the DTR bit of the modem control register. DTR
is placed in the inactive level either as a result of a master reset, during loop mode operation, or clearing the
DTR bit.
INTRPT
30
O
Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four
conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed
out (FIFO mode only), an empty transmitter holding register, or an enabled modem status interrupt. INTRPT
is reset (deactivated) either when the interrupt is serviced or as a result of a master reset.
MR
35
I
Master reset. When active (high), MR clears most ACE registers and sets the levels of various output signals
(see Table 2).
NC
1, 6, 13,
21, 25, 36,
37, 48
I
No connection
OUT1
OUT2
34
31
O
Outputs 1 and 2. These are user-designated output terminals that are set to the active (low) level by setting
respective modem control register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2 are set to inactive the
(high) level as a result of master reset, during loop mode operations, or by clearing bit 2 (OUT1) or bit 3 (OUT2)
of the MCR.
RCLK
5
I
Receiver clock. RCLK is the 16
× baud rate clock for the receiver section of the ACE.


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