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AD773AJD Datenblatt(PDF) 8 Page - Analog Devices |
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AD773AJD Datenblatt(HTML) 8 Page - Analog Devices |
8 / 16 page AD773A REV. 0 –8– REFERENCE INPUT The AD773A’s high impedance reference input allows direct connection with standard voltage references. Unlike the resistor ladder requirements of a flash converter the AD773A’s single pin, high impedance input can be driven from one low cost, low power reference. The high impedance input allows multiple AD773A’s to be driven from one reference thus minimizing drift errors. Figure 11 shows the AD773A connected to the AD680. The AD680 is a single supply, low power, low cost 2.5 V reference with performance specifications ideally suited for the AD773A. The low pass filter minimizes the AD680’s wideband noise. Other recommended 2.5 V references are the AD580 and REF43. AD680 2 GND V IN V OUT 4 6 REF IN REF GND 22 Ω 10 µF 0.1 µF AD773A 2 1 Figure 11. Recommended AD773A to AD680 Connection CLOCK INPUT The AD773A’s pipelined architecture operates on both the rising and falling edges of the clock input. A low jitter, symmetrical clock will provide the highest level of performance. The recommended logic family to drive the clock input is HC. The AD773A’s minimum clock half cycle may necessitate the use of an external divide-by-two circuit as shown in Figure 12. Power dissipation will vary with input clock frequency as shown in Figure 13. +5V R D 74XX74 Q Q S 40MHz +5V CLK Figure 12. Divide-by-Two Clock Circuit 1.07 1.04 1.02 1.03 1.06 1.05 SAMPLE FREQUENCY – Hz 1.5E+07 1.0E+07 2.0E+07 1.08 Figure 13. Power Dissipation vs. Sample Frequency EQUIVALENT ANALOG INPUT CIRCUIT The AD773A equivalent analog input circuit is shown in Figure 14. The typical input bias current is 5 µA, while input capacitance is typically 5 pF. In the single-ended input configuration one input is connected to AGND while the second input is driven to full scale ( ±500 mV). Under nominal conditions the collector of the input transistor is at +1.15 V. This allows signals to be offset by up to +0.65 V without significantly degrading performance. In the negative direction, the emitter of the input transistor should not drop below –1.25 V. Therefore, signals can be offset by –0.65 V without significant performance degradation. Figure 15 shows signal-to-noise ratio vs. common-mode input voltage. +5V 1.0mA +1.15V 1.0mA –5V –1.25V 5pF AIN 1Vp-p AD773A Figure 14. Equivalent Analog Input Circuit 60 0 30 10 20 50 40 AIN = –0.3dB AIN = – 6dB COMMON MODE INPUT VOLTAGE – V 1.0 –1.2 –1.4 0.8 0.4 0.2 0.0 0.6 –0.4 –0.6 –0.8 –1.0 –0.2 Figure 15. S/N+D vs. Common-Mode Input Voltage, fCLK = 20 MSPS |
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