January 2003

Specifications subject to change without notice,contact your sales representatives for the most recent information.

4/26

Preliminary

Ver 1.0

SM79108 01/03

SyncMOS Technologies Inc.

SM79108

Preliminary

Pin Descriptions

40L

PDIP

Pin#

44L

QFP

Pin#

44L

PLCC

Pin#

Symbol

Active

I/O

(GPIO)

Names

1

40

2

P1.0/T2

i/o

bit 0 of port 1 & timer 2 clock out

2

41

3

P1.1/T2EX

i/o

bit 1 of port 1 & timer 2 control

3

42

4

P1.2/SPWM

i/o

bit 2 of port 1 & SPWM channel

4

43

5

P1.3

i/o

bit 3 of port 1

5

44

6

P1.4

i/o

bit 4 of port 1

6

1

7

P1.5/PWM

i/o

bit 5 of port 1 & PWM channel

7

2

8

P1.6

i/o

bit 6 of port 1

8

3

9

P1.7

i/o

bit 7 of port 1

9

4

10

RES

H

i

Reset

10

5

11

P3.0/RXD

i/o

bit 0 of port 3 & receive data

11

7

13

P3.1/TXD

i/o

bit 1 of port 3 & transmit data

12

8

14

P3.2/#INT0

-/L

i/o

bit 2 of port 3 & low true interrupt 0

13

9

15

P3.3/#INT1

-/L

i/o

bit 3 of port 3 & low true interrupt 1

14

10

16

P3.4/T0/ADC0

i/o

bit 4 of port 3 & ADC channel 0 & Timer 0

15

11

17

P3.5/T1/ADC1

i/o

bit 5 of port 3 & ADC channel 1 &Timer 1

16

12

18

P3.6/#WR/ADC2

i/o

bit 6 of port 3 & ADC channel 2 & external memory write

17

13

19

P3.7/#RD/ADC3

i/o

bit 7 of port 3 & ADC channel 3 & external memory read

18

14

20

XTAL2

o

Crystal out

19

15

21

XTAL1

i

Crystal in

20

16

22

VSS

Sink Voltage, Ground

21

18

24

P2.0/A8/COM0

i/o

bit 0 of port 2 & bit 8 of external memory address & LCCD common 0 output

22

19

25

P2.1/A9/COM1

i/o

bit 1 of port 2 & bit 9 of external memory address & LCCD common 1 output

23

20

26

P2.2/A10/COM2

i/o

bit 2 of port 2 & bit 10 of external memory address & LCCD common 2 output

24

21

27

P2.3/A11/COM3

i/o

bit 3 of port 2 & bit 11 of external memory address & LCCD common 3 output

25

22

28

P2.4/A12/SEG0

i/o

bit 4 of port 2 & bit 12 of external memory address & LCCD seg 0 output

26

23

29

P2.5/SEG1

i/o

bit 5 of port 2 & LCCD seg 1 output

27

24

30

P2.6/SEG2

i/o

bit 6 of port 2 & LCCD seg 2 output

28

25

31

P2.7/SEG3

i/o

bit 7 of port 2 & LCCD seg 3 output

29

26

32

#PSEN/SEG4

o

program storage enable & LCCD seg 4 output

30

27

33

ALE/SEG5

o

address latch enable & LCCD seg 5 output

31

29

35

#EA

L

i

external access

32

30

36

P0.7/AD7/SEG6

i/o

bit 7 of port 0 & data/address bit 7 of external memory & LCCD seg 6 output

33

31

37

P0.6/AD6/SEG7

i/o

bit 6 of port 0 & data/address bit 6 of external memory & LCCD seg7 output

34

32

38

P0.5/AD5/SEG8

i/o

bit 5 of port 0 & data/address bit 5 of external memory & LCCD seg 8 output

35

33

39

P0.4/AD4/SEG9

i/o

bit 4 of port 0 & data/address bit 4 of external memory & LCCD seg 9 output

36

34

40

P0.3/AD3/SEG10

i/o

bit 3 of port 0 & data/address bit 3 of external memory & LCCD seg 10 output

37

35

41

P0.2/AD2/SEG11

i/o

bit 2 of port 0 & data/address bit 2 of external memory & LCCD seg 11 output

38

36

42

P0.1/AD1/SEG12

i/o

bit 1 of port 0 & data/address bit 1 of external memory & LCCD seg 12 output

39

37

43

P0.0/AD0/SEG13

i/o

bit 0 of port 0 & data/address bit 0 of external memory & LCCD seg 13 output

40

38

44

VDD

i

Drive Voltage, Vcc

17

23

P4.0

i/o

bit 0 of Port 4

28

34

P4.1

i/o

bit 1 of Port 4

39

1

P4.2

i/o

bit 2 of Port 4

6

12

P4.3

i/o

bit 3 of Port 4