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ADS8406 Datenblatt(PDF) 5 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation. Click here to check the latest version.
Teilenummer ADS8406
Bauteilbeschribung  16-BIT, 1.25 MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICRO POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE
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Hersteller  BURR-BROWN [Burr-Brown (TI)]
Direct Link  http://www.burr-brown.com
Logo BURR-BROWN - Burr-Brown (TI)

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TIMING CHARACTERISTICS
ADS8406
SLAS426A – AUGUST 2004 – REVISED DECEMBER 2004
All specifications typical at –40
°C to 85°C, +VA = +VBD = 5 V (1)(2)(3)
PARAMETER
MIN
TYP
MAX
UNIT
tCONV
Conversion time
500
650
ns
tACQ
Acquisition time
150
ns
tpd1
CONVST low to BUSY high
40
ns
tpd2
Propagation delay time, end of conversion to BUSY low
5
ns
tw1
Pulse duration, CONVST low
20
ns
tsu1
Setup time, CS low to CONVST low
0
ns
tw2
Pulse duration, CONVST high
20
ns
CONVST falling edge jitter
10
ps
tw3
Pulse duration, BUSY signal low
Min(tACQ)
ns
tw4
Pulse duration, BUSY signal high
610
ns
Hold time, First data bus data transition (RD low, or CS low for
th1
40
ns
read cycle, or BYTE input changes) after CONVST low
Delay time, CS low to RD low (or BUSY low to RD low when CS =
td1
0
ns
0)
tsu2
Setup time, RD high to CS high
0
ns
tw5
Pulse duration, RD low time
50
ns
ten
Enable time, RD low (or CS low for read cycle) to data valid
20
ns
td2
Delay time, data hold from RD high
0
ns
td3
Delay time, BYTE rising edge or falling edge to data valid
2
20
ns
tw6
Pulse duration, RD high
20
ns
tw7
Pulse duration, CS high time
20
ns
Hold time, last RD (or CS for read cycle ) rising edge to CONVST
th2
50
ns
falling edge
tsu3
Setup time, BYTE transition to RD falling edge
0
ns
th3
Hold time, BYTE transition to RD falling edge
0
ns
Disable time, RD high (CS high for read cycle) to 3-stated data
tdis
20
ns
bus
td5
Delay time, end of conversion to MSB data valid
10
ns
Byte transition setup time, from BYTE transition to next BYTE
tsu4
50
ns
transition
td6
Delay time, CS rising edge to BUSY falling edge
50
ns
td7
Delay time, BUSY falling edge to CS rising edge
50
ns
Setup time, from the falling edge of CONVST (used to start the
valid conversion) to the next falling edge of CONVST (when CS =
tsu(AB)
60
500
ns
0 and CONVST used to abort) or to the next falling edge of CS
(when CS is used to abort)
Setup time, falling edge of CONVST to read valid data (MSB) from
tsu5
MAX(tCONV) + MAX(td5)
ns
current conversion
Hold time, data (MSB) from previous conversion hold valid from
th4
MIN(tCONV)
ns
falling edge of CONVST
(1)
All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.
(2)
See timing diagrams.
(3)
All timings are measured with 20-pF equivalent loads on all data bits and BUSY pins.
5


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