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CS5466 Datenblatt(PDF) 8 Page - Cirrus Logic |
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CS5466 Datenblatt(HTML) 8 Page - Cirrus Logic |
8 / 16 page CS5466 8 SWITCHING CHARACTERISTICS • Min / Max characteristics and specifications are guaranteed over all Operating Conditions. • Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C. • VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V. • Logic Levels: Logic 0 = 0 V, Logic 1 = VD+. Notes: 10. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF. 11. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. 12. Pulse output timing is specified at MCLK = 4.096 MHz. Current and voltage signals are at unity power factor. Refer to Section 5.3 for more information on pulse output pins. 13. Timing is proportional to the frequency of MCLK. 14. When FREQ2 = 0, FREQ1=1 and FREQ0=1, FOUT will have a typical pulse width of 20 µs at MCLK = 4.096 MHz. Parameter Symbol Min Typ Max Unit Rise Times Any Digital Input (Note 10) Any Digital Output trise - - - 50 1.0 - µs ns Fall Times Any Digital Input (Note 10) Any Digital Output tfall - - - 50 1.0 - µs ns Start-up Oscillator Start-Up Time XTAL = 4.096 MHz (Note 11) tost -60 - ms E1 and E2 Timing (Note 12 and 13) Period t1 500 - ms Pulse Width t2 250 - - ms Rising Edge to Falling Edge t3 250 ms E1 Falling Edge to E2 Falling Edge t4 250 - ms FOUT Timing (Note 12 and 13) Period t5 0.10 1 / fFOUT ms Pulse Width (Note 14) t6 -0.5*t5 90 ms FOUT low t7 -0.5*t5 -ms E1 E2 FOUT t 1 t 2 t 3 t 5 t 6 t 4 t 7 t 3 t 1 t 2 Figure 1. Timing Diagram for E1, E2 and FOUT |
Ähnliche Teilenummer - CS5466 |
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Ähnliche Beschreibung - CS5466 |
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