Am30LV0064D

11

CELL LAYOUT AND ADDRESS ASSIGNMENT

Note: Device programming is executed on a page basis while erase is performed on a block basis. During read operations, data

is transferred from the Flash array to the internal Data Register on a page basis. Data is then sequentially read from the Data

Register on a Byte basis.

Figure 1. Mass Storage Device Cell Layout

Table 1. Address Assignment

Legend:

Notes:

1. A8 is automatically set “Low” or “High” by the 00h or 01h command.

2. A22 to A13 specifies the Block Address, A12 to A9 specifies the Page Address within a block, and A7 to A0 identifies the

byte address within half a page.

I/O 7

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

First Cycle

A7

A6

A5

A4

A3

A2

A1

A0

Second Cycle

A16

A15

A14

A13

A12

A11

A10

A9

Third Cycle

X

X

A22

A21

A20

A19

A18

A17

256

16

16,384 Pages

(1,024 Blocks)

Flash Memory

Array

512 + 16 Byte

Data Register

I/O 7

I/O 0

~

16 Pages

(1 Block)

528 Bytes

(1 Page)

256