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SN74AC533DWR Datenblatt(PDF) 1 Page - Texas Instruments |
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SN74AC533DWR Datenblatt(HTML) 1 Page - Texas Instruments |
1 / 11 page SN54AC533, SN74AC533 OCTAL TRANSPARENT DTYPE LATCHES WITH 3STATE OUTPUTS SCAS555C − NOVEMBER 1995 − REVISED OCTOBER 2003 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 10.5 ns at 5 V D 3-State Inverting Outputs Drive Bus Lines Directly D Full Parallel Access for Loading description/ordering information The ’AC533 devices are octal transparent D-type latches with 3-state outputs. When the latch-enable (LE) input is high, the Q outputs follow the complements of the data (D) inputs. When LE is taken low, the Q outputs are latched at the inverse logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube SN74AC533N SN74AC533N SOIC − DW Tube SN74AC533DW AC533 SOIC − DW Tape and reel SN74AC533DWR AC533 −40 °C to 85°C SOP − NS Tape and reel SN74AC533NSR AC533 −40 C to 85 C SSOP − DB Tape and reel SN74AC533DBR AC533 TSSOP − PW Tube SN74AC533PW AC533 TSSOP − PW Tape and reel SN74AC533PWR AC533 CDIP − J Tube SNJ54AC533J SNJ54AC533J −55 °C to 125°C CFP − W Tube SNJ54AC533W SNJ54AC533W −55 C to 125 C LCCC − FK Tube SNJ54AC533FK SNJ54AC533FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2003, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE SN54AC533 ...J OR W PACKAGE SN74AC533 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) 32 1 20 19 9 10 11 12 13 4 5 6 7 8 18 17 16 15 14 8D 7D 7Q 6Q 6D 2D 2Q 3Q 3D 4D SN54AC533...FK PACKAGE (TOP VIEW) |
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