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CS51411E Datenblatt(PDF) 6 Page - ON Semiconductor |
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CS51411E Datenblatt(HTML) 6 Page - ON Semiconductor |
6 / 16 page CS51411, CS51412, CS51413, CS51414 http://onsemi.com 6 APPLICATIONS INFORMATION THEORY OF OPERATION V2 Control The CS5141X family of buck regulators provides leading edge technology, a high level of integration and high operating frequencies allowing the layout of a switch–mode power supply in a very small board area. These devices are based on the proprietary V2 control architecture. V2 control uses the output voltage and its ripple as the ramp signal, providing an ease of use not generally associated with voltage or current mode control. Improved line regulation, load regulation and very fast transient response are also major advantages. Figure 3. Buck Converter with V2 Control. Buck Controller FFB VREF + Duty Cycle V2 Control Error Amplifier PWM Comparator R1 Oscillator – VO SFB VIN Latch Slope Comp L1 C1 D1 R2 S R VC S1 As shown in Figure 3, there are two voltage feedback paths in V2 control, namely FFB(Fast Feedback) and SFB(Slow Feedback). In FFB path, the feedback voltage connects directly to the PWM comparator. This feedback path carries the ramp signal as well as the output DC voltage. Artificial ramp derived from oscillator is added to the feedback signal to improve stability. The other feedback path SFB connects the feedback voltage to the error amplifier whose output VC feeds to the other input of the PWM comparator. In a constant frequency mode, the oscillator signal sets the output latch and turns on the switch S1. This starts a new switch cycle. The ramp signal, composed of both artificial ramp and output ripple, eventually comes across the VC voltage, and consequently resets the latch to turn off the switch. The switch S1 will turn on again at the beginning of the next switch cycle. In a buck converter, the output ripple is determined by the ripple current of the inductor L1 and the ESR (equivalent series resistor) of the output capacitor C1. The slope compensation signal is a fixed voltage ramp provided by the oscillator. Adding this signal eliminates subharmonic oscillation associated with the operation at duty cycle greater than 50%. The artificial ramp also ensures the proper PWM function when the output ripple voltage is inadequate. The slope compensation signal is properly sized to serve it purposes without sacrificing the transient response speed. Under load and line transient, not only the ramp signal changes, but more significantly the DC component of the feedback voltage varies proportionally to the output voltage. FFB path connects both signals directly to the PWM comparator. This allows instant modulation of the duty cycle to counteract any output voltage deviations. The transient response time is independent of the error amplifier bandwidth. This eliminates the delay associated with error amplifier and greatly improves the transient response time. The error amplifier is used here to ensure excellent DC accuracy. Error Amplifier The CS5141X has a transconductance error amplifier, whose non–inverting input is connected to an Internal Reference Voltage generated from the on–chip regulator. The inverting input connects to the VFB pin. The output of the error amplifier is made available at the VC pin. A typical frequency compensation requires only a 0.1 µF capacitor connected between the VC pin and ground, as shown in Figure 1. This capacitor and error amplifier’s output resistance (approximately 8.0 M Ω) create a low frequency pole to limit the bandwidth. Since V2 control does not require a high bandwidth error amplifier, the frequency compensation is greatly simplified. The VC pin is clamped below Output High Voltage. This allows the regulator to recover quickly from over current or short circuit conditions. Oscillator and Sync Feature (CS51411 and CS51413 only) The on–chip oscillator is trimmed at the factory and requires no external components for frequency control. The high switching frequency allows smaller external components to be used, resulting in a board area and cost savings. The tight frequency tolerance simplifies magnetic components selection. The switching frequency is reduced to 25% of the nominal value when the VFB pin voltage is below Frequency Foldback Threshold. In short circuit or over–load conditions, this reduces the power dissipation of the IC and external components. An external clock signal can sync CS51411/CS51414 to a higher frequency. The rising edge of the sync pulse turns on the power switch to start a new switching cycle, as shown in Figure 4. There is approximately 0.5 µs delay between the rising edge of the sync pulse and rising edge of the VSW pin voltage. The sync threshold is TTL logic compatible, and duty cycle of the sync pulses can vary from 10% to 90%. The |
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Ähnliche Beschreibung - CS51411E |
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